TMS320F28388D: SPI Pull High the CS Line for a Cycle with Transmit Delay?

Hi all!

I am trying to send data with SPI and tx fifo. Basically I just wanna pull the CS high and stop the clock for a cycle between each sendings. Thus I tried to put transmit delays but I didn't get what I want.

When I add 1 cycle delay then CS stays high for half cycle. When CS low again then clk start after 1.5 Half cycle. To sum up; Clk stops for 2 cycle and CS stays high for half cycle between each sending when the transmit delay is 1 cycle.

Similarly, Clk stops for 3 cycle and CS stays high for 1.5 cycle between each sending when the transmit delay is 2 cycle

Can I just stop the clock and pull the CS high for one cycle between each sendings?

Thanks in advance.

My spi init code example.

SPI CLK is 1MHz 16 bit data length and the data is 0xaaaa

void initSPIFIFO()
{
    //
    // Must put SPI into reset before configuring it
    //
    SPI_disableModule(SPIA_BASE);

    //
    // FIFO configuration
    //
    SPI_enableFIFO(SPIA_BASE);
    SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
    SPI_setFIFOInterruptLevel(SPIA_BASE, (SPI_TxFIFOLevel)FIFO_LVL,
                             (SPI_RxFIFOLevel)FIFO_LVL);
    SPI_setTxFifoTransmitDelay(SPIA_BASE, 1);


    //
    // SPI configuration. Use a 1MHz SPICLK and 16-bit word size.
    //
    SPI_setConfig(SPIA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0,
                  SPI_MODE_MASTER, 1000000, 16);
    SPI_enableModule(SPIA_BASE);
}

Fig 1: No Tranmist Delay

Fig 2: 1 Cycle Transmit Delay

Fig 3: 2 Cycle Transmit Delay