Part Number: TMS320F28335
Other Parts Discussed in Thread: UNIFLASH
Hello,
This is the third thread which I opened to run c2000 bootloader.
Please tell me what I have to do to achieve this.
What I did so far is:
1. I created two different project for both bootloader and application.
2. I configured two different linker for both project.
3. I allocated FLASHA for bootloader and seperated rest of sectors for application.
This is the linker of application.
/*
//###########################################################################
//
// FILE: F28335.cmd
//
// TITLE: Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $
// $Release Date: June 8, 2012 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
-l DSP2833x_Headers_nonBIOS.cmd
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28335
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28335 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2_1 : origin = 0x00A000, length = 0x000AA8
PC_TEST_1 : origin = 0x00AAA8, length = 0x000004
RAML2_2 : origin = 0x00AAAC, length = 0x000554
RAML3 : origin = 0x00B000, length = 0x001000
ZONE6 : origin = 0x0100000, length = 0x100000
ZONE7A : origin = 0x0200000, length = 0x00FC00
/* APP_FLASH : origin = 0x300000, length = 0x008000
FLASHG : origin = 0x308000, length = 0x008000
FLASHF_1 : origin = 0x310000, length = 0x005558
FLASHF_2 : origin = 0x315558, length = 0x002AA8
FLASHE : origin = 0x318000, length = 0x008000
FLASHD : origin = 0x320000, length = 0x008000
FLASHC_1 : origin = 0x328000, length = 0x002AAC
FLASHC_2 : origin = 0x32AAAC, length = 0x005554
FLASHB : origin = 0x330000, length = 0x007FFE
APP_BEGIN : origin = 0x337FFE, length = 0x000002
FLASHA : origin = 0x338000, length = 0x007E78*/
APP_FLASH : origin = 0x300000, length = 0x037FFE
APP_BEGIN : origin = 0x337FFE, length = 0x000002
BL_FLASH : origin = 0x338000, length = 0x007E78
PC_TEST_2 : origin = 0x33FE78, length = 0x000004
PC_TEST_3 : origin = 0x33FE7C, length = 0x000004
CRC_TABLE : origin = 0x33FE80, length = 0x000100
CSM_RSVD : origin = 0x33FF80, length = 0x000076
//BL_BEGIN : origin = 0x33FFF6, length = 0x000002
CSM_PWL : origin = 0x33FFF8, length = 0x000008
OTP : origin = 0x380400, length = 0x000400
ADC_CAL : origin = 0x380080, length = 0x000009
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
ROM : origin = 0x3FF27C, length = 0x000D44
RESET : origin = 0x3FFFC0, length = 0x000002
VECTORS : origin = 0x3FFFC2, length = 0x00003E
BOOT_RSVD : origin = 0x000000, length = 0x000050
RAMM0 : origin = 0x000050, length = 0x0003B0
RAMM1 : origin = 0x000400, length = 0x000400
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : {} > APP_FLASH, PAGE = 0
.pinit : {} > APP_FLASH, PAGE = 0
.text : {} > APP_FLASH, PAGE = 0
codestart : {} > APP_BEGIN PAGE = 0
Flash28_API:
{
-l Flash28335_API_V210.lib(.econst)
-l Flash28335_API_V210.lib(.text)
}
LOAD = APP_FLASH,
RUN = RAML0,
LOAD_START(_Flash28_API_LoadStart),
LOAD_END(_Flash28_API_LoadEnd),
RUN_START(_Flash28_API_RunStart),
PAGE = 0
ramfuncs : LOAD = APP_FLASH,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
psa_crc : LOAD = APP_FLASH,
RUN = RAML0,
LOAD_START(_PSA_CRCLoadStart),
LOAD_END(_PSA_CRCLoadEnd),
RUN_START(_PSA_CRCRunStart),
RUN_END(_PSA_CRCRunEnd),
LOAD_SIZE(_PSA_CRCLoadSize),
PAGE = 0
pc_test_section_1 : LOAD = APP_FLASH,
RUN = PC_TEST_1,
LOAD_START(_PC_Test1LoadStart),
LOAD_END(_PC_Test1LoadEnd),
RUN_START(_PC_Test1RunStart),
RUN_END(_PC_Test1RunEnd),
LOAD_SIZE(_PC_Test1LoadSize),
PAGE = 0
pc_test_section_2 : > PC_TEST_2, PAGE = 0
pc_test_section_3 : > PC_TEST_3, PAGE = 0
STL_Test_utility : > RAMM1, PAGE = 0
STL_psa_crc_vars : > RAMM1, PAGE = 0
STL_crc_test_data : > APP_FLASH, PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
STL_CRC_calc : > APP_FLASH, PAGE = 0
STL_CRC_TABLE : > CRC_TABLE, PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0 PAGE = 0
.ebss : > RAML4 PAGE = 0
.esysmem : > RAMM1 PAGE = 0
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : {} > APP_FLASH, PAGE = 0
.switch : {} > APP_FLASH, PAGE = 0
/* Allocate IQ math areas: */
IQmath : {} > APP_FLASH, PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 0
DMARAML5 : > RAML5, PAGE = 0
DMARAML6 : > RAML6, PAGE = 0
DMARAML7 : > RAML7, PAGE = 0
/* Allocate 0x400 of XINTF Zone 7 to storing data */
ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
This is the linker of bootloader.
/*
//###########################################################################
//
// FILE: F28335.cmd
//
// TITLE: Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $
// $Release Date: June 8, 2012 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
-l DSP2833x_Headers_nonBIOS.cmd
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28335
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28335 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2_1 : origin = 0x00A000, length = 0x000AA8
PC_TEST_1 : origin = 0x00AAA8, length = 0x000004
RAML2_2 : origin = 0x00AAAC, length = 0x000554
RAML3 : origin = 0x00B000, length = 0x001000
ZONE6 : origin = 0x0100000, length = 0x100000
ZONE7A : origin = 0x0200000, length = 0x00FC00
/* APP_FLASH : origin = 0x300000, length = 0x008000
FLASHG : origin = 0x308000, length = 0x008000
FLASHF_1 : origin = 0x310000, length = 0x005558
FLASHF_2 : origin = 0x315558, length = 0x002AA8
FLASHE : origin = 0x318000, length = 0x008000
FLASHD : origin = 0x320000, length = 0x008000
FLASHC_1 : origin = 0x328000, length = 0x002AAC
FLASHC_2 : origin = 0x32AAAC, length = 0x005554
FLASHB : origin = 0x330000, length = 0x007FFE
APP_BEGIN : origin = 0x337FFE, length = 0x000002
FLASHA : origin = 0x338000, length = 0x007E78*/
APP_FLASH : origin = 0x300000, length = 0x037FFE
//APP_BEGIN : origin = 0x337FFE, length = 0x000002
BL_FLASH : origin = 0x338000, length = 0x007E78
PC_TEST_2 : origin = 0x33FE78, length = 0x000004
PC_TEST_3 : origin = 0x33FE7C, length = 0x000004
CRC_TABLE : origin = 0x33FE80, length = 0x000100
CSM_RSVD : origin = 0x33FF80, length = 0x000076
BL_BEGIN : origin = 0x33FFF6, length = 0x000002
CSM_PWL : origin = 0x33FFF8, length = 0x000008
OTP : origin = 0x380400, length = 0x000400
ADC_CAL : origin = 0x380080, length = 0x000009
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
ROM : origin = 0x3FF27C, length = 0x000D44
RESET : origin = 0x3FFFC0, length = 0x000002
VECTORS : origin = 0x3FFFC2, length = 0x00003E
BOOT_RSVD : origin = 0x000000, length = 0x000050
RAMM0 : origin = 0x000050, length = 0x0003B0
RAMM1 : origin = 0x000400, length = 0x000400
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : {} > BL_FLASH, PAGE = 0
.pinit : {} > BL_FLASH, PAGE = 0
.text : {} > BL_FLASH, PAGE = 0
codestart : {} > BL_BEGIN PAGE = 0
Flash28_API:
{
-l Flash28335_API_V210.lib(.econst)
-l Flash28335_API_V210.lib(.text)
}
LOAD = BL_FLASH,
RUN = RAML0,
LOAD_START(_Flash28_API_LoadStart),
LOAD_END(_Flash28_API_LoadEnd),
RUN_START(_Flash28_API_RunStart),
PAGE = 0
ramfuncs : LOAD = BL_FLASH,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
psa_crc : LOAD = BL_FLASH,
RUN = RAML0,
LOAD_START(_PSA_CRCLoadStart),
LOAD_END(_PSA_CRCLoadEnd),
RUN_START(_PSA_CRCRunStart),
RUN_END(_PSA_CRCRunEnd),
LOAD_SIZE(_PSA_CRCLoadSize),
PAGE = 0
pc_test_section_1 : LOAD = BL_FLASH,
RUN = PC_TEST_1,
LOAD_START(_PC_Test1LoadStart),
LOAD_END(_PC_Test1LoadEnd),
RUN_START(_PC_Test1RunStart),
RUN_END(_PC_Test1RunEnd),
LOAD_SIZE(_PC_Test1LoadSize),
PAGE = 0
pc_test_section_2 : > PC_TEST_2, PAGE = 0
pc_test_section_3 : > PC_TEST_3, PAGE = 0
STL_Test_utility : > RAMM1, PAGE = 0
STL_psa_crc_vars : > RAMM1, PAGE = 0
STL_crc_test_data : > BL_FLASH, PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
STL_CRC_calc : > BL_FLASH, PAGE = 0
STL_CRC_TABLE : > CRC_TABLE, PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0 PAGE = 0
.ebss : > RAML4 PAGE = 0
.esysmem : > RAMM1 PAGE = 0
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : {} > BL_FLASH, PAGE = 0
.switch : {} > BL_FLASH, PAGE = 0
/* Allocate IQ math areas: */
IQmath : {} > BL_FLASH PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 0
DMARAML5 : > RAML5, PAGE = 0
DMARAML6 : > RAML6, PAGE = 0
DMARAML7 : > RAML7, PAGE = 0
/* Allocate 0x400 of XINTF Zone 7 to storing data */
ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
3. I left same 0x33FFF6 entry point for bootloader in the linker, and I allocated 0x337FFE for application entry point in application linker.
4. I download the app from starting from 0x300000 to 0x300000+CodeSize. CodeSize:42kB
5. After completing bootloader process. I used this asm code asm ( " LB 0x337FFE ") to jump application.
0x337FFE is last two address of FLASHB and I never write anything these address as you see in the 4.step.
Therefore, when I want to jump this enrty point. It is always empty and falls illegal ISR.
I really do not understand how we expect to find any information in the address that we allocated as entry point in application linker
although I do not write anything there while flashing the app.
Guys, it's been a month that I am struggling with this and it becomes really boring.
