• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 481 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F2812 XREADY

Frank D'Aliesio
Intellectual 715 points

Other Parts Discussed in Thread: TMS320F2812

My customer is confused on designing for XREADY.  They will use XREADY from a slow peripheral that will take much longer than any internally programmable active phase, but they may not have much data setup time to the DSP after XREADY does go high.  So they are trying to better understand what happens after XREADY is sampled high at the DSP. What is the soonest that the DSP would latch in read data after sampling it high? The timing diagrams 6-32 and 6-33 are very confusing on this. What does the WS mean in the diagram?  They did not find the statements "then the access will complete" to be very clear...

Thank you,

Frank

  • 0
    Intellectual 715 points

    Also request overshoot and undershoot tolerance (TMS320F2812) information for the digital pins for  the same processor as above . we understand the DC input specs, but as is common in digital designs, there may be short time over- and under-shoots on bus and other lines.

    Thank you,

    Frank

  • 0
    TI__Guru* 84731 points

    Hi Frank,

    There are some more diagrams in the XINTF peripheral User's Guide for that device that may also help: spru067c

    WS is the number of wait states that are inserted by hardware when using the XREADY - see spru067c section 3 Table 1. Basically this is the number of wait-states that the CPU has added in response to sampling a low XREADY signal - so basically it is a value that will depend on your external peripheral and how long it is holding XREADY low. The table shows how the added wait-states from XREADY affect the duration of your Active period for reads and writes in terms of XTIMCLK cycles.

    As for what happens after XREADY is sampled high, I would look at Figure 11 and Figure 12 of spru067c. As you can see, for synchronous XREADY the data will become valid on the following XTIMCLK cycle. For asynchronous XREADY, the data will become valid on the third following XTIMCLK cycle. "Then the access will complete" simply means the remainder of the access ( the last cycle of your active period, your trail time etc.) happens as usual according to your XINTF settings.

    I hope this helps clear things up!

    Regards,

    Katie