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TMS320F28388D: SPI communication

aruna revanna
Prodigy 170 points
Part Number: TMS320F28388D

Hello

I did SPI configuration as follows

uint16_t sData = 0;
uint16_t rData = 0;

//mySPI0 initialization
SPI_disableModule(mySPI0_BASE);
SPI_setConfig(mySPI0_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1,//SPIc,DEVICE_LSPCLK_FREQ=50MHZ,//! Mode 1. Polarity 0, phase 1. Rising edge with delay.
SPI_MODE_MASTER, 1000000, 8); //SPI master mode,8-bit data width
//SPI_disableFIFO(mySPI0_BASE);
SPI_enableFIFO(mySPI0_BASE);//Enables the transmit and receive FIFOs.
SPI_enableLoopback(mySPI0_BASE);
SPI_setEmulationMode(mySPI0_BASE, SPI_EMULATION_FREE_RUN);////!Set so breakpoints don't disturb xmission
SPI_enableModule(mySPI0_BASE);

I am transmitting and receiving the data by enabling loopback.

sData = 0x0a0b;

SPI_writeDataBlockingFIFO(mySPI0_BASE, sData); //FIFO enabled
x = SPI_getTxFIFOStatus(mySPI0_BASE);
rData = SPI_readDataBlockingFIFO(mySPI0_BASE); //FIFO enabled

I have question regarding SPI_setConfig()  function,in this function I am setting data width as 8 bit.

so as per SPI_setConfig() function explanation lower 8 bits data should get discarded and only upper 8 bits data I should receive.

but  received data is  rData=0x0b0a.

so rather then getting only 0x000a data why received data is 0x0b0a?

Thanks in advance

  • 0
    TI__Guru 55700 points

    Aruna,

    When the character length of SPI transaction is less than 16bits, you need to left shift. In your case, you're trying to initiate SPI transaction of 1 byte (8bits), so you need to left shift byte by 8 bits as shown below.

    charLength = 8;

    SPI_writeDataBlockingNonFIFO(base, data << (16U - charLength));

    We also have ready made function to transmit a byte. Please check SPI_transmitByte function available in driverlib function.This function automatically take care of left shift etc for you.

    SPI_transmitByte(base, txData)

    Please refer spi_ex6_eeprom example which uses these functions.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Prodigy 170 points

    Hello,

    Can any of you help me understand the difference between the below two functions and in which scenario which should I use?

    1)SPI_writeDataNonBlocking 2)SPI_writeDataBlockingFIFO

    same way for, read case also.

    Regards,
    Jay

  • 0 in reply to Jainam Shah
    TI__Guru 55700 points

    Jay,

    SPI_writeDataBlockingFIFO - Wait was for the FIFO to have some space before writing to SPI transmit buffer

    SPI_writeDataNonBlocking   - This function doesn't check whether FIFO is empty (or) not. It directly write to SPI transmit buffer

    SPI_readDataBlockingFIFO - Waits until RX FIFO isn't empty before read SPI receive buffer

    SPI_readDataNonBlocking   - This function doesn't check whether RX FIFO has any received content (or) not. It just does read of 

                                                      SPI Receive buffer

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Prodigy 170 points

    I am a little confused about the transmit/receive sequence of operation in FIFO mode,

    Can you please elaborate on it?

    Regards,
    Jay

  • 0 in reply to Jainam Shah
    TI__Guru 55700 points

    Jay,

    This is open-ended question. What exactly is your confusion?

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Prodigy 170 points

    Yeah, according to my understanding,  FIFO transmission array is first filled then as it reaches to FIFO interrupt level(full level) interrupt will be generated and then we put data from the FIFO array to transmit buffer to transmit data 

    and at receiving end, as receiving FIFO reaches to FIFO full level, interrupt will generate and we read the data from receiving FIFO receiving array

    Is this how the operation is carried out or I am missing something?

    Regards,
    Jay

  • 0 in reply to Jainam Shah
    TI__Guru 55700 points

    Jay,

    Jainam Shah said:
    FIFO transmission array is first filled then as it reaches to FIFO interrupt level(full level) interrupt will be generated and then we put data from the FIFO array to transmit buffer to transmit data 

    No, When number of words to TX FIFO is less than TXFFIL (TXFFST < = TXFFIL), interrupt is generated.

    Jainam Shah said:
    at receiving end, as receiving FIFO reaches to FIFO full level, interrupt will generate and we read the data from receiving FIFO receiving array

    Yes, your understanding is correct.

    Regards,

    Manoj