TMS320F28388D: ADC sampling application

Hi Johnny,

If the application goals are highest possible resolution and lowest possible noise, definitely they should be looking to use 16-bit differential sampling. 

16-bit conversions take about 1us and there are 4 ADCs that can operate in parallel, so certainly there is time to oversample 2x in the control loop.  You just have to weigh whether the additional latency to take 2 samples and average them together instead of taking 1 sample is worth the additional noise reduction.  

For the average output current, does the sampling rate need to be slower?  It will probably be easier (and there should be time) to just sample the 4 phase currents + 1 average current every 5us. You can average over three 5us periods if needed. 

So overall, the fast sampling is probably something like this:

• ADC-A: SOC0 = i1, SOC1 = i1 , SOC2 = average current
• ADC-B: SOC0 = i2, SOC1 = i2 
• ADC-C: SOC0 = i3, SOC1 = i3 
• ADC-D: SOC0 = i4, SOC1 = i4 

And each ISR you'd average SOC0 and SOC1 together.  Each ISR you'd also add the average current to a sum, and then every 3rd ISR divide to get your overall average current.

Adding in the slower OTP samples kinda depends on the requirements.  Do these also need to be 16-bit resolution?  Do they need to be as low-noise as possible (differential) or are they going to be single-ended inputs?  

Hi Devin,

Sorry for replying late. I just catch up and know more about the customer's application these few days cause Chinese New Year holiday.

Here is the customer's first version of the design information.

Currently, the 4 phase currents are all sampled by a 16-bit differential sampling ADC (ADC-A) and sampled every 5us.

Also, for the average output current, the sampling rate is every 15us.

It is a good suggestion from you to sample and operate in parallel for the customer's next layout revision. 

How about adding in the slower OTP samples ? There are also 4 OTP signal sampled every 1ms, though it is not necessary to need the 16-bit resolution.

However, in my understanding, it is not supported to configure few channels of any single ADC's as 12 bit single-ended and 16-bit differential at the same time, correct ? If so, 4 OTP signals may also need to be 16-bit resolution.

How about arrange the sampling sequence in something like that ?

• ADC-A: SOC0 = i1, SOC1 = i1, SOC2 = average current, SOC3 = OTP1
• ADC-B: SOC0 = i2, SOC1 = i2                                         , SOC3 = OTP2
• ADC-C: SOC0 = i3, SOC1 = i3                                         , SOC3 = OTP3
• ADC-D: SOC0 = i4, SOC1 = i4                                         , SOC3 = OTP4

Thanks for any comment. I appreciate it.

Hi Johnny,

You want to avoid running the ADCs in a way that isn't in lock-step if you are using 16-bit ADC (see TRM section "ensuring synchronous operation").  This would include dedicating one or more ADCs as 12-bit and some other ADCs as 16-bit and then triggering them at the same time (12-bit and 16-bit ADCs have different timings, so they won't run synchronously). 

It is OK to dedicate some ADCs as 12-bit and some ADCs as 16-bit as long as they aren't running at the same time, so one solution would be to distribute the 4 phase currents and the average current among say 3 ADCs (set in 16-bit differential mode) and the 4 OTP samples to another ADC running in 12-bit single-ended mode.  You'd then use a delayed ePWM trigger for the 12-bit ADC that occurs after the 16-bit samples have completed:

• ADC-A (16-bit DE): SOC0 = (i1, ePWM1A), SOC2 = (i4, ePWM1A), SOC3 = (i1, ePWM1A) 
• ADC-B (16-bit DE): SOC0 = (i2, ePWM1A), SOC2 = (i4, ePWM1A), SOC3 = (i2, ePWM1A) 
• ADC-C (16-bit DE): SOC0 = (i3, ePWM1A), SOC2 = (avg, ePWM1A), SOC3 = (i3, ePWM1A) 
• ADC-D (12-bit SE): SOC0 = (OTP1, ePWM1B), SOC2 = (OTP2, ePWM1B), SOC3 = (OTP3, ePWM1B), SOC4 = (OTP4, ePWM1B)  

Notes:

• ePWM1B trigger has the ePWM CMP set such that it occurs 3us (or however long is needed for the longest 16-bit sample chain) after ePWM1A trigger
• You can use "burst mode" to get ADC-D to only convert one of the SOCs each trigger instead of always converting all 4
• Note: If ePWM1 doesn't have a spare compare, you can use a spare ePWM module that is sync'ed to ePWM1 to generate the delayed trigger.  You could also devise a scheme where one ePWM is running much slower (but still synchronized) such that the OTP signals are sampled at a much lower rate
• In the above channel allocation, i4 is sampled simultaneously on two ADCs, then averaged.  This will average out noise in the ADC, but not externally (if some noise occurs in the input, both ADCs will likely capture it since they are sampling at the same time).  Channels 14 + 15 connect to all ADCs internally to achieve this. This scheme was selected to get the average time of all 4 phases to align (and it also makes the average current reading align too)

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Another possibility would be to manually take OTP samples every once in a while in the ADC ISR:

• (assuming all 16-bit conversions are complete when the ISR is entered)
• Check if it is time to trigger once in 1ms OTP samples, if yes:
  • Swap the modes of all the ADCs to 12-bit single-ended mode
  • Trigger (ideally simultaneously) all 4 ADCs to convert the one OTP signal each
• Collect and process the data from the 4 phase currents and 1 average current
• If OTP samples were taken this time
  • Wait until OTP samples complete (normal ISR processing time above is probably enough since one 12-bit sample is only ~300ns)
  • Process OTP samples
  • Switch ADCs back to 16-bit differential resolution
• Normal ISR cleanup

Note: the setAdcMode function takes quite awhile because it swapps out the best linearity and offset trim between 12-bit and 16-bit modes.  12-bit performance is still very good if you leave the 16-bit trims in, so feel free to directly toggle the resolution and signalmode bits to save time if needed. 

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Finally, if you want to use 16-bit mode for the OTP samples, note that you can run some ADCs in 16-bit differential mode at the same time other ADCs run in 16-bit single-ended mode (timings are identical) so you can always put all the OTP signals on say ADC-D and then do something like:

• ADC-A (16-bit DE): SOC0 = (i1, ePWM1A), SOC2 = (i4, ePWM1A), SOC3 = (i1, ePWM1A) 
• ADC-B (16-bit DE): SOC0 = (i2, ePWM1A), SOC2 = (i4, ePWM1A), SOC3 = (i2, ePWM1A) 
• ADC-C (16-bit DE): SOC0 = (i3, ePWM1A), SOC2 = (avg, ePWM1A), SOC3 = (i3, ePWM1A) 
• ADC-D (16-bit SE): SOC0 = (OTP1, ePWM1B), SOC2 = (OTP2, ePWM1B), SOC3 = (OTP3, ePWM1B), SOC4 = (OTP4, ePWM1B)  

This will just result in the OTP signals being sampled at a high rate which may not be desirable if you want to keep the signal conditioning circuitry cheap by using a "charge-sharing" driver design...see https://www.ti.com/lit/an/spracv0/spracv0.pdf