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LAUNCHXL-F28379D: Porting SCIA Echo Loopback to RAM Management Example

Djony Pamudji
Prodigy 185 points
Part Number: LAUNCHXL-F28379D
Other Parts Discussed in Thread: C2000WARE,

Hi, 

I have a working SCIA function to print "Hello World" message on terminal console. All functions :  scia_fifo_init(); // Initialize the SCI FIFO
scia_echoback_init(), scia_msg(msg), and GPIO_SetupPinMux() are tested to be working fine for SCI baud rate of 115200. 

When I ported over this SCIA function to RAM_Management project, somehow the baud rate of 115200 does not work any more. I saw some random characters printed out on the console, suggesting the clock frequency get changed by routines but I could not find which functions might change the clock. Attached is my modified code. 

Fullscreen RAM_management_cpu01.c Download 
//###########################################################################
//
// FILE:   RAM_management_cpu01.c
//
// TITLE:  RAM management Example for F2837xD.
//
//! \addtogroup dual_example_list
//! <h1> Shared RAM management (RAM_management) </h1>
//!
//! This example shows how to assign shared RAM for use by both the CPU02 and
//! CPU01 core.
//! Shared RAM regions are defined in  both the CPU02 and CPU01 linker files.
//! In this example GS0 and GS14 are assigned to/owned by CPU02. The remaining
//! shared RAM regions are owned by CPU01.
//! In this example:
//!
//! A pattern is written to c1_r_w_array and then IPC flag is sent to notify
//! CPU02 that data is ready to be read. CPU02 then reads the data from
//! c2_r_array and writes a modified pattern to c2_r_w_array. Once CPU02
//! acknowledges the IPC flag to , CPU01 reads the data from c1_r_array and
//! compares with expected result.
//!
//! A Timed ISR is also serviced in both CPUs. The ISRs are copied into the
//! shared RAM region owned by the respective CPUs. Each ISR toggles a GPIO.
//! Watch GPIO31 and GPIO34 on oscilloscope. If using the control card watch
//! LED1 and LED2 blink at different rates.
//!
//!  - c1_r_w_array[] is mapped to shared RAM GS1
//!  - c1_r_array[]   is mapped to shared RAM GS0
//!  - c2_r_array[]   is mapped to shared RAM GS1
//!  - c2_r_w_array[] is mapped to shared RAM GS0
//!  - cpu_timer0_isr in CPU02 is copied to shared RAM GS14 , toggles GPIO31
//!  - cpu_timer0_isr in CPU01 is copied to shared RAM GS15 , toggles GPIO34
//!
//! \b  Watch \b Variables
//!  - error Indicates that the data written is not correctly received by the
//!    other CPU.
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.12.00.00 $
// $Release Date: Fri Feb 12 19:03:23 IST 2021 $
// $Copyright:
// Copyright (C) 2013-2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"
#include "F2837xD_Ipc_drivers.h"

//
// Globals
//
uint16_t c1_r_array[256];   // mapped to GS0 of shared RAM owned by CPU02
uint16_t c1_r_w_array[256]; // mapped to GS1 of shared RAM owned by CPU01
#pragma DATA_SECTION(c1_r_array,"SHARERAMGS0");
#pragma DATA_SECTION(c1_r_w_array,"SHARERAMGS1");

uint16_t error;
uint16_t multiplier;

extern uint16_t isrfuncLoadStart;
extern uint16_t isrfuncLoadEnd;
extern uint16_t isrfuncRunStart;
extern uint16_t isrfuncLoadSize;

//
// Function Prototypes
//
__interrupt void cpu_timer0_isr(void);
#pragma CODE_SECTION(cpu_timer0_isr,"isrfunc")

void Shared_Ram_dataRead_c1(void);
void Shared_Ram_dataWrite_c1(void);
void scia_echoback_init(void);
void scia_fifo_init(void);
void scia_xmit(int a);
void scia_msg(char *msg);

//
// Main
//
void main(void)
{
    char *msg;
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

#ifdef _STANDALONE
#ifdef _FLASH
    //
    //  Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);
#else
    //
    //  Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_RAM);
#endif
#endif

//
// Step 2. Initialize GPIO:
//
    InitGpio();

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the __interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();
//
//  Setup for SCIA
    GPIO_SetupPinMux(43, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(43, GPIO_INPUT, GPIO_PUSHPULL);
    GPIO_SetupPinMux(42, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(42, GPIO_OUTPUT, GPIO_ASYNC);

    scia_fifo_init();       // Initialize the SCI FIFO
    scia_echoback_init();   // Initialize SCI for echoback

    msg = "\r\n\n\nHello World!\0";
    scia_msg(msg);

//
// Give GPIO31 Control to CPU02
//
    GPIO_SetupPinMux(31,GPIO_MUX_CPU2,0);
    GPIO_SetupPinOptions(31, GPIO_OUTPUT,0);

//
// Give GPIO34 Control to CPU01
//
    GPIO_SetupPinMux(34,GPIO_MUX_CPU1,0);
    GPIO_SetupPinOptions(34, GPIO_OUTPUT,0);

//
// Give Memory Access to GS0/ GS14 SARAM to CPU02
//
    while( !(MemCfgRegs.GSxMSEL.bit.MSEL_GS0 &
             MemCfgRegs.GSxMSEL.bit.MSEL_GS14))
    {
        EALLOW;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS0 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS14 = 1;
        EDIS;
    }

//
//  Copy ISR routine to a specified RAM location to determine the size
//
    memcpy(&isrfuncRunStart, &isrfuncLoadStart, (uint32_t)&isrfuncLoadSize);

//
// Wait until
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.TIMER0_INT = &cpu_timer0_isr;
    EDIS;    // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripheral. This function can be
//         found in F2837xD_CpuTimers.c
//
    InitCpuTimers();   // For this example, only initialize the Cpu Timers

//
// Configure CPU-Timer0 to interrupt every second:
// c2_FREQ in MHz, 2 second Period (in uSeconds)
//
    ConfigCpuTimer(&CpuTimer0, 200, 2000000);

//
// To ensure precise timing, use write-only instructions to write to the
// entire register.
//
    CpuTimer0Regs.TCR.all = 0x4000;

//
// Enable CPU int1 which is connected to CPU-Timer 0
//
    IER |= M_INT1;

//
// Enable TINT0 in the PIE: Group 1 interrupt 7
//
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;   // Enable Global interrupt INTM
    ERTM;   // Enable Global realtime interrupt DBGM

    error = 0;
    multiplier = 0;

    Shared_Ram_dataWrite_c1();
    IPCLtoRFlagSet(IPC_FLAG10);

    while(1)
    {
        //
        // If there is no pending flag
        //
        if(IPCLtoRFlagBusy(IPC_FLAG10) == 0)
        {
            Shared_Ram_dataRead_c1();

            if(multiplier++ > 255)
            {
                multiplier = 0;
            }

            //
            // Write an array to a memory location owned by CPU01
            //
            Shared_Ram_dataWrite_c1();

            //
            // Set a flag to notify CPU02 that data is available
            //
            IPCLtoRFlagSet(IPC_FLAG10);
        }
    }
}

//
// cpu_timer0_isr - CPU Timer0 ISR
//
__interrupt void cpu_timer0_isr(void)
{
   EALLOW;
   CpuTimer0.InterruptCount++;
   GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1;
   EDIS;

   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// Shared_Ram_dataWrite_c1 - Write a pattern to an array in shared RAM
//
void Shared_Ram_dataWrite_c1(void)
{
    uint16_t index;

    //
    // Use first location to write a multiplier.
    //
    c1_r_w_array[0] = multiplier;

    for(index = 1; index < 256; index++)
    {
        c1_r_w_array[index] = index;

        //
        //the following code will attempt to write to a shared RAM
        //assigned to cpu2 and as a result will cause an error.
        //
        //c1_r_array[index] = 1000 + index;
    }
}

//
// Shared_Ram_dataRead_c1 - Read and compare an array from shared RAM
//
void Shared_Ram_dataRead_c1(void)
{
    uint16_t index;

    if(c1_r_array[0] == multiplier)
    {
       for(index = 1; index < 256; index++)
       {
           if(c1_r_array[index] != multiplier*c1_r_w_array[index])
           {
               error = 1;
           }
       }
    }
    else
    {
        error = 1;
    }
}
//
//  scia_echoback_init - Test 1,SCIA  DLB, 8-bit word, baud rate 0x000F,
//                       default, 1 STOP bit, no parity
//
void scia_echoback_init()
{
    //
    // Note: Clocks were turned on to the SCIA peripheral
    // in the InitSysCtrl() function
    //

    SciaRegs.SCICCR.all = 0x0007;   // 1 stop bit,  No loopback
                                    // No parity,8 char bits,
                                    // async mode, idle-line protocol
    SciaRegs.SCICTL1.all = 0x0003;  // enable TX, RX, internal SCICLK,
                                    // Disable RX ERR, SLEEP, TXWAKE
    SciaRegs.SCICTL2.all = 0x0003;
    SciaRegs.SCICTL2.bit.TXINTENA = 1;
    SciaRegs.SCICTL2.bit.RXBKINTENA = 1;

    //
    // SCI baud rate = LSPCLK / ((BRR+1)*8) , where BRR is between 0 to 65535
    // BRR = (LSPCLK/(8 * SCI baud rate)) - 1;
    // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B.
    // @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.
    //
    // SCIA at 9600 baud --> BRR = 651 = 0x28B
    // SciaRegs.SCIHBAUD.all = 0x0002;
    // SciaRegs.SCILBAUD.all = 0x008B;

    // SCIA at 115200 baud --> BRR = 54 - 1 = 53 = 0x35
    SciaRegs.SCIHBAUD.all = 0x0000;
    SciaRegs.SCILBAUD.all = 0x0035;

    SciaRegs.SCICTL1.all = 0x0023;  // Relinquish SCI from Reset
}
//
// scia_xmit - Transmit a character from the SCI
//
void scia_xmit(int a)
{
    while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}
    SciaRegs.SCITXBUF.all =a;
}
//
// scia_msg - Transmit message via SCIA
//
void scia_msg(char * msg)
{
    int i;
    i = 0;
    while(msg[i] != '\0')
    {
        scia_xmit(msg[i]);
        i++;
    }
}
//
// scia_fifo_init - Initialize the SCI FIFO
//
void scia_fifo_init()
{
    SciaRegs.SCIFFTX.all = 0xE040;
    SciaRegs.SCIFFRX.all = 0x2044;
    SciaRegs.SCIFFCT.all = 0x0;
}
//
// End of file
//

  • 0
    TI__Mastermind 19795 points

    Hi,

    Thanks for your question! Could you provide a bit more detail on the use-case for this porting of an SCI function to RAM management is?

    As much detail as you can provide would be greatly helpful. Things like system-level reasoning for using the RAM management for a communication block, etc.

    Thanks!

    Vince

  • 0 in reply to Vince
    Prodigy 185 points

    Hi Vince, 

    Basically we want to use SCI function for debugging purposes, i.e. : to be able to send the value of variable to the terminal console for verification. This is required because the current CCS debug mode does not update the debug variable in real-time, causing it difficult to debug and we cannot rely on the value shown in the debug window. 

    Thank you. 

    Djony 

  • 0 in reply to Djony Pamudji
    TI__Expert 7985 points

    Hi Djony, 

    Hope you have been able to resolve this issue.  If not, can you please advise if the interface is working at any baud rate?  In order to enable us to assist you more efficiently and expeditiously, we will need a simplified test case from you that demonstrates the issue you are facing.  Will you be able to provide a test case? 

    Regards, 

    Krishna

  • 0 in reply to Krishna Allam
    Prodigy 185 points

    Hi Krishna, as a matter of fact, I did not change much on the RAM_Management project except adding the SCI initialization from line 173 to 183 (10 lines of additional code)  as follows : 

    // Setup for SCIA
    GPIO_SetupPinMux(43, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(43, GPIO_INPUT, GPIO_PUSHPULL);
    GPIO_SetupPinMux(42, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(42, GPIO_OUTPUT, GPIO_ASYNC);

    scia_fifo_init(); // Initialize the SCI FIFO
    scia_echoback_init(); // Initialize SCI for echoback

    msg = "\r\n\n\nHello World!\0";
    scia_msg(msg);

    By right, the SCI code has been configured for baudrate 115200 (SYSCLK = 200 MHz, LSPCLK = 50 MHz). 

    Somehow after inserting the SCI code into RAM_Management project, the baudrate is no longer 115200. I believe this is not an issue of SCI module, but somehow the RAM_Management project changes either SYSCLK or LSPCLK frequency which I could not pin point which function or what has caused the clock frequency get changed. 

  • 0 in reply to Djony Pamudji
    TI__Expert 7985 points

    Hi Djony, 

    Can you please advise if the interface is working at any baud rate?  In order to enable us to assist you more efficiently and expeditiously, we will need a simplified test case from you that demonstrates the issue you are facing.  Will you be able to provide a test case? 

    Regards, 

    Krishna

  • 0 in reply to Krishna Allam
    Prodigy 185 points

    Hi Krishna, 

    The SCI code itself runs well on any baud rate. I have verified it at least for 9600 and 115200 baud on both LSPCLK set to 50 MHz and 100 MHz with SYSCLK at 200 MHz. By right, there should be an issue with the SCI code and interface port. 

    The problem comes only when we port the working SCI code into this RAM_Management project. Attached is the output shown on the console. 

    This RAM_Management project is the sample code provided in C2000 Ware library. 

  • 0 in reply to Djony Pamudji
    TI__Expert 7985 points

    Thanks Djony that is good information.  Please let us know all the tools that you are using, CCS version, Compiler version, C2000Ware version.  Are you using a controlCARD as your target.  Please elaborate a bit on the target hardware as well and we will ensure it get routed appropriately. 

    Regards,

    Krishna

  • 0 in reply to Krishna Allam
    Prodigy 185 points

    CCS version = 10.4.0

    C2000Ware version = 3_04_00_00

    Compiler version = TI v20.2.5.LTS

    LAUNCHXL_28379D

    ZOC Terminal Emulator for PC, or any terminal software  

  • 0
    Prodigy 185 points

    Part Number: LAUNCHXL-F28379D

    I applied this formula in calculating the SCI baud rate divider register value :  BRR = (LSPCLK/(8 * SCI baud rate)) - 1; 

    Using SYSCLK = 200 MHz, and LSPCLK = 50 MHz, for baud rate 115200, the BRR = 53 = 0x35 

    Verified using project example :  sci_echoback_cpu01, the above BRR to be correct and the SCI code is working fine.

    But when the same SCI code ported to the example project : RAM_Management, the actual baud rate somehow 

    becomes half of the intended 115200, i.e. : 57600 only.  Question : why does it become half  ?! 

    Below is my overall code for reference : 

    //###########################################################################
    //
    // FILE: RAM_management_cpu01.c
    //
    // TITLE: RAM management Example for F2837xD.
    //
    //! \addtogroup dual_example_list
    //! <h1> Shared RAM management (RAM_management) </h1>
    //!
    //! This example shows how to assign shared RAM for use by both the CPU02 and
    //! CPU01 core.
    //! Shared RAM regions are defined in both the CPU02 and CPU01 linker files.
    //! In this example GS0 and GS14 are assigned to/owned by CPU02. The remaining
    //! shared RAM regions are owned by CPU01.
    //! In this example:
    //!
    //! A pattern is written to c1_r_w_array and then IPC flag is sent to notify
    //! CPU02 that data is ready to be read. CPU02 then reads the data from
    //! c2_r_array and writes a modified pattern to c2_r_w_array. Once CPU02
    //! acknowledges the IPC flag to , CPU01 reads the data from c1_r_array and
    //! compares with expected result.
    //!
    //! A Timed ISR is also serviced in both CPUs. The ISRs are copied into the
    //! shared RAM region owned by the respective CPUs. Each ISR toggles a GPIO.
    //! Watch GPIO31 and GPIO34 on oscilloscope. If using the control card watch
    //! LED1 and LED2 blink at different rates.
    //!
    //! - c1_r_w_array[] is mapped to shared RAM GS1
    //! - c1_r_array[] is mapped to shared RAM GS0
    //! - c2_r_array[] is mapped to shared RAM GS1
    //! - c2_r_w_array[] is mapped to shared RAM GS0
    //! - cpu_timer0_isr in CPU02 is copied to shared RAM GS14 , toggles GPIO31
    //! - cpu_timer0_isr in CPU01 is copied to shared RAM GS15 , toggles GPIO34
    //!
    //! \b Watch \b Variables
    //! - error Indicates that the data written is not correctly received by the
    //! other CPU.
    //!
    //
    //###########################################################################
    // $TI Release: F2837xD Support Library v3.12.00.00 $
    // $Release Date: Fri Feb 12 19:03:23 IST 2021 $
    // $Copyright:
    // Copyright (C) 2013-2021 Texas Instruments Incorporated - http://www.ti.com/
    //
    // Redistribution and use in source and binary forms, with or without
    // modification, are permitted provided that the following conditions
    // are met:
    //
    // Redistributions of source code must retain the above copyright
    // notice, this list of conditions and the following disclaimer.
    //
    // Redistributions in binary form must reproduce the above copyright
    // notice, this list of conditions and the following disclaimer in the
    // documentation and/or other materials provided with the
    // distribution.
    //
    // Neither the name of Texas Instruments Incorporated nor the names of
    // its contributors may be used to endorse or promote products derived
    // from this software without specific prior written permission.
    //
    // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    // $
    //###########################################################################

    //
    // Included Files
    //
    #include "F28x_Project.h"
    #include "F2837xD_Ipc_drivers.h"

    //
    // Globals
    //
    uint16_t c1_r_array[256]; // mapped to GS0 of shared RAM owned by CPU02
    uint16_t c1_r_w_array[256]; // mapped to GS1 of shared RAM owned by CPU01
    #pragma DATA_SECTION(c1_r_array,"SHARERAMGS0");
    #pragma DATA_SECTION(c1_r_w_array,"SHARERAMGS1");

    uint16_t error;
    uint16_t multiplier;

    extern uint16_t isrfuncLoadStart;
    extern uint16_t isrfuncLoadEnd;
    extern uint16_t isrfuncRunStart;
    extern uint16_t isrfuncLoadSize;

    //
    // Function Prototypes
    //
    __interrupt void cpu_timer0_isr(void);
    #pragma CODE_SECTION(cpu_timer0_isr,"isrfunc")

    void Shared_Ram_dataRead_c1(void);
    void Shared_Ram_dataWrite_c1(void);
    void scia_echoback_init(void);
    void scia_fifo_init(void);
    void scia_xmit(int a);
    void scia_msg(char *msg);

    //
    // Main
    //
    void main(void)
    {
    char *msg;
    //
    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the F2837xD_SysCtrl.c file.
    //
    InitSysCtrl();

    #ifdef _STANDALONE
    #ifdef _FLASH
    //
    // Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);
    #else
    //
    // Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_RAM);
    #endif
    #endif

    //
    // Step 2. Initialize GPIO:
    //
    InitGpio();

    //
    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts
    //
    DINT;

    //
    // Initialize PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.
    // This function is found in the F2837xD_PieCtrl.c file.
    //
    InitPieCtrl();
    //
    // Disable CPU interrupts and clear all CPU interrupt flags:
    //
    IER = 0x0000;
    IFR = 0x0000;

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    // This will populate the entire table, even if the __interrupt
    // is not used in this example. This is useful for debug purposes.
    // The shell ISR routines are found in F2837xD_DefaultIsr.c.
    // This function is found in F2837xD_PieVect.c.
    //
    InitPieVectTable();
    //
    // Setup for SCIA
    GPIO_SetupPinMux(43, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(43, GPIO_INPUT, GPIO_PUSHPULL);
    GPIO_SetupPinMux(42, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(42, GPIO_OUTPUT, GPIO_ASYNC);

    scia_fifo_init(); // Initialize the SCI FIFO
    scia_echoback_init(); // Initialize SCI for echoback

    msg = "\r\n\n\nHello World!\0";
    scia_msg(msg);

    //
    // Give GPIO31 Control to CPU02
    //
    GPIO_SetupPinMux(31,GPIO_MUX_CPU2,0);
    GPIO_SetupPinOptions(31, GPIO_OUTPUT,0);

    //
    // Give GPIO34 Control to CPU01
    //
    GPIO_SetupPinMux(34,GPIO_MUX_CPU1,0);
    GPIO_SetupPinOptions(34, GPIO_OUTPUT,0);

    //
    // Give Memory Access to GS0/ GS14 SARAM to CPU02
    //
    while( !(MemCfgRegs.GSxMSEL.bit.MSEL_GS0 &
    MemCfgRegs.GSxMSEL.bit.MSEL_GS14))
    {
    EALLOW;
    MemCfgRegs.GSxMSEL.bit.MSEL_GS0 = 1;
    MemCfgRegs.GSxMSEL.bit.MSEL_GS14 = 1;
    EDIS;
    }

    //
    // Copy ISR routine to a specified RAM location to determine the size
    //
    memcpy(&isrfuncRunStart, &isrfuncLoadStart, (uint32_t)&isrfuncLoadSize);

    //
    // Wait until
    // Interrupts that are used in this example are re-mapped to
    // ISR functions found within this file.
    //
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.TIMER0_INT = &cpu_timer0_isr;
    EDIS; // This is needed to disable write to EALLOW protected registers

    //
    // Step 4. Initialize the Device Peripheral. This function can be
    // found in F2837xD_CpuTimers.c
    //
    InitCpuTimers(); // For this example, only initialize the Cpu Timers

    //
    // Configure CPU-Timer0 to interrupt every second:
    // c2_FREQ in MHz, 2 second Period (in uSeconds)
    //
    ConfigCpuTimer(&CpuTimer0, 200, 2000000);

    //
    // To ensure precise timing, use write-only instructions to write to the
    // entire register.
    //
    CpuTimer0Regs.TCR.all = 0x4000;

    //
    // Enable CPU int1 which is connected to CPU-Timer 0
    //
    IER |= M_INT1;

    //
    // Enable TINT0 in the PIE: Group 1 interrupt 7
    //
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;

    //
    // Enable global Interrupts and higher priority real-time debug events:
    //
    EINT; // Enable Global interrupt INTM
    ERTM; // Enable Global realtime interrupt DBGM

    error = 0;
    multiplier = 0;

    Shared_Ram_dataWrite_c1();
    IPCLtoRFlagSet(IPC_FLAG10);

    while(1)
    {
    //
    // If there is no pending flag
    //
    if(IPCLtoRFlagBusy(IPC_FLAG10) == 0)
    {
    Shared_Ram_dataRead_c1();

    if(multiplier++ > 255)
    {
    multiplier = 0;
    }

    //
    // Write an array to a memory location owned by CPU01
    //
    Shared_Ram_dataWrite_c1();

    //
    // Set a flag to notify CPU02 that data is available
    //
    IPCLtoRFlagSet(IPC_FLAG10);
    }
    }
    }

    //
    // cpu_timer0_isr - CPU Timer0 ISR
    //
    __interrupt void cpu_timer0_isr(void)
    {
    EALLOW;
    CpuTimer0.InterruptCount++;
    GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1;
    EDIS;

    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
    }

    //
    // Shared_Ram_dataWrite_c1 - Write a pattern to an array in shared RAM
    //
    void Shared_Ram_dataWrite_c1(void)
    {
    uint16_t index;

    //
    // Use first location to write a multiplier.
    //
    c1_r_w_array[0] = multiplier;

    for(index = 1; index < 256; index++)
    {
    c1_r_w_array[index] = index;

    //
    //the following code will attempt to write to a shared RAM
    //assigned to cpu2 and as a result will cause an error.
    //
    //c1_r_array[index] = 1000 + index;
    }
    }

    //
    // Shared_Ram_dataRead_c1 - Read and compare an array from shared RAM
    //
    void Shared_Ram_dataRead_c1(void)
    {
    uint16_t index;

    if(c1_r_array[0] == multiplier)
    {
    for(index = 1; index < 256; index++)
    {
    if(c1_r_array[index] != multiplier*c1_r_w_array[index])
    {
    error = 1;
    }
    }
    }
    else
    {
    error = 1;
    }
    }
    //
    // scia_echoback_init - Test 1,SCIA DLB, 8-bit word, baud rate 0x000F,
    // default, 1 STOP bit, no parity
    //
    void scia_echoback_init()
    {
    //
    // Note: Clocks were turned on to the SCIA peripheral
    // in the InitSysCtrl() function
    //

    SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
    // No parity,8 char bits,
    // async mode, idle-line protocol
    SciaRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,
    // Disable RX ERR, SLEEP, TXWAKE
    SciaRegs.SCICTL2.all = 0x0003;
    SciaRegs.SCICTL2.bit.TXINTENA = 1;
    SciaRegs.SCICTL2.bit.RXBKINTENA = 1;

    //
    // SCI baud rate = LSPCLK / ((BRR+1)*8) , where BRR is between 0 to 65535
    // BRR = (LSPCLK/(8 * SCI baud rate)) - 1;
    // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B.
    // @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.
    //
    // SCIA at 9600 baud --> BRR = 651 = 0x28B
    // SciaRegs.SCIHBAUD.all = 0x0002;
    // SciaRegs.SCILBAUD.all = 0x008B;

    // SCIA at 115200 baud for LSCLK = 100 MHz --> BRR = 108 - 1 = 107 = 0x6B
    // SciaRegs.SCIHBAUD.all = 0x0000;
    // SciaRegs.SCILBAUD.all = 0x006B;

    // SCIA at 115200 baud for LSCLK = 50 MHz --> BRR = 54 - 1 = 53 = 0x35
    SciaRegs.SCIHBAUD.all = 0x0000;
    SciaRegs.SCILBAUD.all = 0x0035;

    SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
    }
    //
    // scia_xmit - Transmit a character from the SCI
    //
    void scia_xmit(int a)
    {
    while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}
    SciaRegs.SCITXBUF.all =a;
    }
    //
    // scia_msg - Transmit message via SCIA
    //
    void scia_msg(char * msg)
    {
    int i;
    i = 0;
    while(msg[i] != '\0')
    {
    scia_xmit(msg[i]);
    i++;
    }
    }
    //
    // scia_fifo_init - Initialize the SCI FIFO
    //
    void scia_fifo_init()
    {
    SciaRegs.SCIFFTX.all = 0xE040;
    SciaRegs.SCIFFRX.all = 0x2044;
    SciaRegs.SCIFFCT.all = 0x0;
    }
    //
    // End of file
    //

    Fullscreen 0407.RAM_management_cpu01.c Download 
    //###########################################################################
//
// FILE:   RAM_management_cpu01.c
//
// TITLE:  RAM management Example for F2837xD.
//
//! \addtogroup dual_example_list
//! <h1> Shared RAM management (RAM_management) </h1>
//!
//! This example shows how to assign shared RAM for use by both the CPU02 and
//! CPU01 core.
//! Shared RAM regions are defined in  both the CPU02 and CPU01 linker files.
//! In this example GS0 and GS14 are assigned to/owned by CPU02. The remaining
//! shared RAM regions are owned by CPU01.
//! In this example:
//!
//! A pattern is written to c1_r_w_array and then IPC flag is sent to notify
//! CPU02 that data is ready to be read. CPU02 then reads the data from
//! c2_r_array and writes a modified pattern to c2_r_w_array. Once CPU02
//! acknowledges the IPC flag to , CPU01 reads the data from c1_r_array and
//! compares with expected result.
//!
//! A Timed ISR is also serviced in both CPUs. The ISRs are copied into the
//! shared RAM region owned by the respective CPUs. Each ISR toggles a GPIO.
//! Watch GPIO31 and GPIO34 on oscilloscope. If using the control card watch
//! LED1 and LED2 blink at different rates.
//!
//!  - c1_r_w_array[] is mapped to shared RAM GS1
//!  - c1_r_array[]   is mapped to shared RAM GS0
//!  - c2_r_array[]   is mapped to shared RAM GS1
//!  - c2_r_w_array[] is mapped to shared RAM GS0
//!  - cpu_timer0_isr in CPU02 is copied to shared RAM GS14 , toggles GPIO31
//!  - cpu_timer0_isr in CPU01 is copied to shared RAM GS15 , toggles GPIO34
//!
//! \b  Watch \b Variables
//!  - error Indicates that the data written is not correctly received by the
//!    other CPU.
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.12.00.00 $
// $Release Date: Fri Feb 12 19:03:23 IST 2021 $
// $Copyright:
// Copyright (C) 2013-2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"
#include "F2837xD_Ipc_drivers.h"

//
// Globals
//
uint16_t c1_r_array[256];   // mapped to GS0 of shared RAM owned by CPU02
uint16_t c1_r_w_array[256]; // mapped to GS1 of shared RAM owned by CPU01
#pragma DATA_SECTION(c1_r_array,"SHARERAMGS0");
#pragma DATA_SECTION(c1_r_w_array,"SHARERAMGS1");

uint16_t error;
uint16_t multiplier;

extern uint16_t isrfuncLoadStart;
extern uint16_t isrfuncLoadEnd;
extern uint16_t isrfuncRunStart;
extern uint16_t isrfuncLoadSize;

//
// Function Prototypes
//
__interrupt void cpu_timer0_isr(void);
#pragma CODE_SECTION(cpu_timer0_isr,"isrfunc")

void Shared_Ram_dataRead_c1(void);
void Shared_Ram_dataWrite_c1(void);
void scia_echoback_init(void);
void scia_fifo_init(void);
void scia_xmit(int a);
void scia_msg(char *msg);

//
// Main
//
void main(void)
{
    char *msg;
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

#ifdef _STANDALONE
#ifdef _FLASH
    //
    //  Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);
#else
    //
    //  Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_RAM);
#endif
#endif

//
// Step 2. Initialize GPIO:
//
    InitGpio();

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the __interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();
//
//  Setup for SCIA
    GPIO_SetupPinMux(43, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(43, GPIO_INPUT, GPIO_PUSHPULL);
    GPIO_SetupPinMux(42, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(42, GPIO_OUTPUT, GPIO_ASYNC);

    scia_fifo_init();       // Initialize the SCI FIFO
    scia_echoback_init();   // Initialize SCI for echoback

    msg = "\r\n\n\nHello World!\0";
    scia_msg(msg);

//
// Give GPIO31 Control to CPU02
//
    GPIO_SetupPinMux(31,GPIO_MUX_CPU2,0);
    GPIO_SetupPinOptions(31, GPIO_OUTPUT,0);

//
// Give GPIO34 Control to CPU01
//
    GPIO_SetupPinMux(34,GPIO_MUX_CPU1,0);
    GPIO_SetupPinOptions(34, GPIO_OUTPUT,0);

//
// Give Memory Access to GS0/ GS14 SARAM to CPU02
//
    while( !(MemCfgRegs.GSxMSEL.bit.MSEL_GS0 &
             MemCfgRegs.GSxMSEL.bit.MSEL_GS14))
    {
        EALLOW;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS0 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS14 = 1;
        EDIS;
    }

//
//  Copy ISR routine to a specified RAM location to determine the size
//
    memcpy(&isrfuncRunStart, &isrfuncLoadStart, (uint32_t)&isrfuncLoadSize);

//
// Wait until
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.TIMER0_INT = &cpu_timer0_isr;
    EDIS;    // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripheral. This function can be
//         found in F2837xD_CpuTimers.c
//
    InitCpuTimers();   // For this example, only initialize the Cpu Timers

//
// Configure CPU-Timer0 to interrupt every second:
// c2_FREQ in MHz, 2 second Period (in uSeconds)
//
    ConfigCpuTimer(&CpuTimer0, 200, 2000000);

//
// To ensure precise timing, use write-only instructions to write to the
// entire register.
//
    CpuTimer0Regs.TCR.all = 0x4000;

//
// Enable CPU int1 which is connected to CPU-Timer 0
//
    IER |= M_INT1;

//
// Enable TINT0 in the PIE: Group 1 interrupt 7
//
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;   // Enable Global interrupt INTM
    ERTM;   // Enable Global realtime interrupt DBGM

    error = 0;
    multiplier = 0;

    Shared_Ram_dataWrite_c1();
    IPCLtoRFlagSet(IPC_FLAG10);

    while(1)
    {
        //
        // If there is no pending flag
        //
        if(IPCLtoRFlagBusy(IPC_FLAG10) == 0)
        {
            Shared_Ram_dataRead_c1();

            if(multiplier++ > 255)
            {
                multiplier = 0;
            }

            //
            // Write an array to a memory location owned by CPU01
            //
            Shared_Ram_dataWrite_c1();

            //
            // Set a flag to notify CPU02 that data is available
            //
            IPCLtoRFlagSet(IPC_FLAG10);
        }
    }
}

//
// cpu_timer0_isr - CPU Timer0 ISR
//
__interrupt void cpu_timer0_isr(void)
{
   EALLOW;
   CpuTimer0.InterruptCount++;
   GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1;
   EDIS;

   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// Shared_Ram_dataWrite_c1 - Write a pattern to an array in shared RAM
//
void Shared_Ram_dataWrite_c1(void)
{
    uint16_t index;

    //
    // Use first location to write a multiplier.
    //
    c1_r_w_array[0] = multiplier;

    for(index = 1; index < 256; index++)
    {
        c1_r_w_array[index] = index;

        //
        //the following code will attempt to write to a shared RAM
        //assigned to cpu2 and as a result will cause an error.
        //
        //c1_r_array[index] = 1000 + index;
    }
}

//
// Shared_Ram_dataRead_c1 - Read and compare an array from shared RAM
//
void Shared_Ram_dataRead_c1(void)
{
    uint16_t index;

    if(c1_r_array[0] == multiplier)
    {
       for(index = 1; index < 256; index++)
       {
           if(c1_r_array[index] != multiplier*c1_r_w_array[index])
           {
               error = 1;
           }
       }
    }
    else
    {
        error = 1;
    }
}
//
//  scia_echoback_init - Test 1,SCIA  DLB, 8-bit word, baud rate 0x000F,
//                       default, 1 STOP bit, no parity
//
void scia_echoback_init()
{
    //
    // Note: Clocks were turned on to the SCIA peripheral
    // in the InitSysCtrl() function
    //

    SciaRegs.SCICCR.all = 0x0007;   // 1 stop bit,  No loopback
                                    // No parity,8 char bits,
                                    // async mode, idle-line protocol
    SciaRegs.SCICTL1.all = 0x0003;  // enable TX, RX, internal SCICLK,
                                    // Disable RX ERR, SLEEP, TXWAKE
    SciaRegs.SCICTL2.all = 0x0003;
    SciaRegs.SCICTL2.bit.TXINTENA = 1;
    SciaRegs.SCICTL2.bit.RXBKINTENA = 1;

    //
    // SCI baud rate = LSPCLK / ((BRR+1)*8) , where BRR is between 0 to 65535
    // BRR = (LSPCLK/(8 * SCI baud rate)) - 1;
    // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B.
    // @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.
    //
    // SCIA at 9600 baud --> BRR = 651 = 0x28B
    // SciaRegs.SCIHBAUD.all = 0x0002;
    // SciaRegs.SCILBAUD.all = 0x008B;

    // SCIA at 115200 baud for LSCLK = 100 MHz --> BRR = 108 - 1 = 107 = 0x6B
    // SciaRegs.SCIHBAUD.all = 0x0000;
    // SciaRegs.SCILBAUD.all = 0x006B;

    // SCIA at 115200 baud for LSCLK = 50 MHz --> BRR = 54 - 1 = 53 = 0x35
    SciaRegs.SCIHBAUD.all = 0x0000;
    SciaRegs.SCILBAUD.all = 0x0035;

    SciaRegs.SCICTL1.all = 0x0023;  // Relinquish SCI from Reset
}
//
// scia_xmit - Transmit a character from the SCI
//
void scia_xmit(int a)
{
    while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}
    SciaRegs.SCITXBUF.all =a;
}
//
// scia_msg - Transmit message via SCIA
//
void scia_msg(char * msg)
{
    int i;
    i = 0;
    while(msg[i] != '\0')
    {
        scia_xmit(msg[i]);
        i++;
    }
}
//
// scia_fifo_init - Initialize the SCI FIFO
//
void scia_fifo_init()
{
    SciaRegs.SCIFFTX.all = 0xE040;
    SciaRegs.SCIFFRX.all = 0x2044;
    SciaRegs.SCIFFCT.all = 0x0;
}
//
// End of file
//

  • 0 in reply to Djony Pamudji
    TI__Mastermind 36085 points

    Hi, 

    Can you try running the example "sci_echoback" located in <C2000Ware>\device_support\f2837xd\examples\cpu1\sci_echoback? Also can you use the following code for GPIO pins 

    GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
    GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
    GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
    GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);

    Best Regards

    Siddharth

  • 0 in reply to Siddharth Deshpande
    TI__Mastermind 19795 points

    Hi Djony,

    I have merged your thread as it is a duplicate of this thread. Please try to keep this discussion to a single thread, thanks!

    Regards,

    Vince

  • 0 in reply to Siddharth Deshpande
    Prodigy 185 points

    Hi Siddharth, 

    I verified the example "sci_echoback" located in C2000Ware to be working fine, except that the GPIO setting needs to be modified to the following : 

    // Setup for SCIA
    GPIO_SetupPinMux(43, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(43, GPIO_INPUT, GPIO_PUSHPULL);
    GPIO_SetupPinMux(42, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(42, GPIO_OUTPUT, GPIO_ASYNC);

    Reason being the GPIO85/84 were not wired out in LAUNCHXL_F28379D (see attached schematics). 

    GPIO43/42 were used instead. 

     

    Hope this clarifies. 

    Best regards, 

    Djony 

  • 0 in reply to Djony Pamudji
    TI__Mastermind 36085 points

    Djony,

    Please try defining the symbol " _LAUNCHXL_F28379D" in your project and run it again.  

    The PLL is configured differently for the Control Card and the Launchpad and hence the arguments to the InitSysPll function are different for both these boards. 

    Best Regards

    Siddharth

  • 0 in reply to Siddharth Deshpande
    Prodigy 185 points

    Hi Siddharth, we have made sure that the symbol "_LAUNCHXL_F28379D" is used on both projects (sci_echoback as well as RAM_Management). Take note that in this experiment, we do not use Control CARD.  Can I suggest that you also run the "RAM_Management" project on your side and see if you can reproduce the issue we are seeing here ?  The testcase is very simple. You just need to import the "RAM_Management" project from C2000Ware Example and replace the "RAM_management_cpu01.c" with the one I am attaching here. 

    Fullscreen 7142.RAM_management_cpu01.c Download 
    //###########################################################################
//
// FILE:   RAM_management_cpu01.c
//
// TITLE:  RAM management Example for F2837xD.
//
//! \addtogroup dual_example_list
//! <h1> Shared RAM management (RAM_management) </h1>
//!
//! This example shows how to assign shared RAM for use by both the CPU02 and
//! CPU01 core.
//! Shared RAM regions are defined in  both the CPU02 and CPU01 linker files.
//! In this example GS0 and GS14 are assigned to/owned by CPU02. The remaining
//! shared RAM regions are owned by CPU01.
//! In this example:
//!
//! A pattern is written to c1_r_w_array and then IPC flag is sent to notify
//! CPU02 that data is ready to be read. CPU02 then reads the data from
//! c2_r_array and writes a modified pattern to c2_r_w_array. Once CPU02
//! acknowledges the IPC flag to , CPU01 reads the data from c1_r_array and
//! compares with expected result.
//!
//! A Timed ISR is also serviced in both CPUs. The ISRs are copied into the
//! shared RAM region owned by the respective CPUs. Each ISR toggles a GPIO.
//! Watch GPIO31 and GPIO34 on oscilloscope. If using the control card watch
//! LED1 and LED2 blink at different rates.
//!
//!  - c1_r_w_array[] is mapped to shared RAM GS1
//!  - c1_r_array[]   is mapped to shared RAM GS0
//!  - c2_r_array[]   is mapped to shared RAM GS1
//!  - c2_r_w_array[] is mapped to shared RAM GS0
//!  - cpu_timer0_isr in CPU02 is copied to shared RAM GS14 , toggles GPIO31
//!  - cpu_timer0_isr in CPU01 is copied to shared RAM GS15 , toggles GPIO34
//!
//! \b  Watch \b Variables
//!  - error Indicates that the data written is not correctly received by the
//!    other CPU.
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.12.00.00 $
// $Release Date: Fri Feb 12 19:03:23 IST 2021 $
// $Copyright:
// Copyright (C) 2013-2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"
#include "F2837xD_Ipc_drivers.h"

//
// Globals
//
uint16_t c1_r_array[256];   // mapped to GS0 of shared RAM owned by CPU02
uint16_t c1_r_w_array[256]; // mapped to GS1 of shared RAM owned by CPU01
#pragma DATA_SECTION(c1_r_array,"SHARERAMGS0");
#pragma DATA_SECTION(c1_r_w_array,"SHARERAMGS1");

uint16_t error;
uint16_t multiplier;

extern uint16_t isrfuncLoadStart;
extern uint16_t isrfuncLoadEnd;
extern uint16_t isrfuncRunStart;
extern uint16_t isrfuncLoadSize;

//
// Function Prototypes
//
__interrupt void cpu_timer0_isr(void);
#pragma CODE_SECTION(cpu_timer0_isr,"isrfunc")

void Shared_Ram_dataRead_c1(void);
void Shared_Ram_dataWrite_c1(void);
void scia_echoback_init(void);
void scia_fifo_init(void);
void scia_xmit(int a);
void scia_msg(char *msg);

//
// Main
//
void main(void)
{
    char *msg;
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

#ifdef _STANDALONE
#ifdef _FLASH
    //
    //  Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);
#else
    //
    //  Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_RAM);
#endif
#endif

//
// Step 2. Initialize GPIO:
//
    InitGpio();

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the __interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();
//
//  Setup for SCIA
    GPIO_SetupPinMux(43, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(43, GPIO_INPUT, GPIO_PUSHPULL);
    GPIO_SetupPinMux(42, GPIO_MUX_CPU1, 15);
    GPIO_SetupPinOptions(42, GPIO_OUTPUT, GPIO_ASYNC);

    scia_fifo_init();       // Initialize the SCI FIFO
    scia_echoback_init();   // Initialize SCI for echoback

    msg = "\r\n\n\nHello World!\0";
    scia_msg(msg);

//
// Give GPIO31 Control to CPU02
//
    GPIO_SetupPinMux(31,GPIO_MUX_CPU2,0);
    GPIO_SetupPinOptions(31, GPIO_OUTPUT,0);

//
// Give GPIO34 Control to CPU01
//
    GPIO_SetupPinMux(34,GPIO_MUX_CPU1,0);
    GPIO_SetupPinOptions(34, GPIO_OUTPUT,0);

//
// Give Memory Access to GS0/ GS14 SARAM to CPU02
//
    while( !(MemCfgRegs.GSxMSEL.bit.MSEL_GS0 &
             MemCfgRegs.GSxMSEL.bit.MSEL_GS14))
    {
        EALLOW;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS0 = 1;
        MemCfgRegs.GSxMSEL.bit.MSEL_GS14 = 1;
        EDIS;
    }

//
//  Copy ISR routine to a specified RAM location to determine the size
//
    memcpy(&isrfuncRunStart, &isrfuncLoadStart, (uint32_t)&isrfuncLoadSize);

//
// Wait until
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.TIMER0_INT = &cpu_timer0_isr;
    EDIS;    // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripheral. This function can be
//         found in F2837xD_CpuTimers.c
//
    InitCpuTimers();   // For this example, only initialize the Cpu Timers

//
// Configure CPU-Timer0 to interrupt every second:
// c2_FREQ in MHz, 2 second Period (in uSeconds)
//
    ConfigCpuTimer(&CpuTimer0, 200, 2000000);

//
// To ensure precise timing, use write-only instructions to write to the
// entire register.
//
    CpuTimer0Regs.TCR.all = 0x4000;

//
// Enable CPU int1 which is connected to CPU-Timer 0
//
    IER |= M_INT1;

//
// Enable TINT0 in the PIE: Group 1 interrupt 7
//
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;   // Enable Global interrupt INTM
    ERTM;   // Enable Global realtime interrupt DBGM

    error = 0;
    multiplier = 0;

    Shared_Ram_dataWrite_c1();
    IPCLtoRFlagSet(IPC_FLAG10);

    while(1)
    {
        //
        // If there is no pending flag
        //
        if(IPCLtoRFlagBusy(IPC_FLAG10) == 0)
        {
            Shared_Ram_dataRead_c1();

            if(multiplier++ > 255)
            {
                multiplier = 0;
            }

            //
            // Write an array to a memory location owned by CPU01
            //
            Shared_Ram_dataWrite_c1();

            //
            // Set a flag to notify CPU02 that data is available
            //
            IPCLtoRFlagSet(IPC_FLAG10);
        }
    }
}

//
// cpu_timer0_isr - CPU Timer0 ISR
//
__interrupt void cpu_timer0_isr(void)
{
   EALLOW;
   CpuTimer0.InterruptCount++;
   GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1;
   EDIS;

   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// Shared_Ram_dataWrite_c1 - Write a pattern to an array in shared RAM
//
void Shared_Ram_dataWrite_c1(void)
{
    uint16_t index;

    //
    // Use first location to write a multiplier.
    //
    c1_r_w_array[0] = multiplier;

    for(index = 1; index < 256; index++)
    {
        c1_r_w_array[index] = index;

        //
        //the following code will attempt to write to a shared RAM
        //assigned to cpu2 and as a result will cause an error.
        //
        //c1_r_array[index] = 1000 + index;
    }
}

//
// Shared_Ram_dataRead_c1 - Read and compare an array from shared RAM
//
void Shared_Ram_dataRead_c1(void)
{
    uint16_t index;

    if(c1_r_array[0] == multiplier)
    {
       for(index = 1; index < 256; index++)
       {
           if(c1_r_array[index] != multiplier*c1_r_w_array[index])
           {
               error = 1;
           }
       }
    }
    else
    {
        error = 1;
    }
}
//
//  scia_echoback_init - Test 1,SCIA  DLB, 8-bit word, baud rate 0x000F,
//                       default, 1 STOP bit, no parity
//
void scia_echoback_init()
{
    //
    // Note: Clocks were turned on to the SCIA peripheral
    // in the InitSysCtrl() function
    //

    SciaRegs.SCICCR.all = 0x0007;   // 1 stop bit,  No loopback
                                    // No parity,8 char bits,
                                    // async mode, idle-line protocol
    SciaRegs.SCICTL1.all = 0x0003;  // enable TX, RX, internal SCICLK,
                                    // Disable RX ERR, SLEEP, TXWAKE
    SciaRegs.SCICTL2.all = 0x0003;
    SciaRegs.SCICTL2.bit.TXINTENA = 1;
    SciaRegs.SCICTL2.bit.RXBKINTENA = 1;

    //
    // SCI baud rate = LSPCLK / ((BRR+1)*8) , where BRR is between 0 to 65535
    // BRR = (LSPCLK/(8 * SCI baud rate)) - 1;
    // @LSPCLK = 50 MHz (200 MHz SYSCLK) HBAUD = 0x02 and LBAUD = 0x8B.
    // @LSPCLK = 30 MHz (120 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x86.
    //
    // SCIA at 9600 baud --> BRR = 651 = 0x28B
    // SciaRegs.SCIHBAUD.all = 0x0002;
    // SciaRegs.SCILBAUD.all = 0x008B;

    // SCIA at 115200 baud for LSCLK = 100 MHz --> BRR = 108 - 1 = 107 = 0x6B
    // SciaRegs.SCIHBAUD.all = 0x0000;
    // SciaRegs.SCILBAUD.all = 0x006B;

    // SCIA at 115200 baud for LSCLK = 50 MHz --> BRR = 54 - 1 = 53 = 0x35
    SciaRegs.SCIHBAUD.all = 0x0000;
    SciaRegs.SCILBAUD.all = 0x0035;

    SciaRegs.SCICTL1.all = 0x0023;  // Relinquish SCI from Reset
}
//
// scia_xmit - Transmit a character from the SCI
//
void scia_xmit(int a)
{
    while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}
    SciaRegs.SCITXBUF.all =a;
}
//
// scia_msg - Transmit message via SCIA
//
void scia_msg(char * msg)
{
    int i;
    i = 0;
    while(msg[i] != '\0')
    {
        scia_xmit(msg[i]);
        i++;
    }
}
//
// scia_fifo_init - Initialize the SCI FIFO
//
void scia_fifo_init()
{
    SciaRegs.SCIFFTX.all = 0xE040;
    SciaRegs.SCIFFRX.all = 0x2044;
    SciaRegs.SCIFFCT.all = 0x0;
}
//
// End of file
//

    We really saw an issue here that the actual SCI baud rate becomes half of the intended one. It is not something like GPIO pin muxing or clock programming mistakes. We want to know what could be the cause of halving baud rate. Is it because of  dual CPUs or what ? 

    Thank you. 

    Best regards, Djony Pamudji 

  • 0 in reply to Djony Pamudji
    TI__Mastermind 36085 points

    Djony,

    Will run it on the Launchpad and keeo you posted.

    Best Regards

    Siddharth

  • +1 in reply to Siddharth Deshpande
    Prodigy 185 points

    Hi Siddharth,

    I just realized that we have added the pre-defined symbol wrongly as "_LAUNCHXL_28379D" instead of "_LAUNCHXL_F28379D".  After get it corrected, now the SCIA code is working fine. Sorry for our mistake which has caused false alarm. 

    Best regards, 

    Djony