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TMS320F280025C: SCI communication: Rx FiFo reading issue for an AT command Response of more than 16 characters (Rx Overflow)

Part Number: TMS320F280025C
Other Parts Discussed in Thread: C2000WARE

HI !

I am using the F280025C uC as a master to communicate through SCI(UART) with a WiFi module to send and receive the AT commands and their responses.

I am using the Tx FiFo and Rx FiFo interrupts to acheive the same. Since the AT commnads and their corresponding response is an array of characters, I have modified the SCI_writeCharArray and SCI_ReadCharArray  accordingly for my application. 

The interrupts functions and the Responses to AT commnads work as I want, as long the length doesn´t exceed the maximum FiFo length which is 16. When the response is more than 16 characters which is most of the times, FiFo overflow occurs and I can only read the last 16 characters where the first ones are lost. 

The Rx interrupt looks as below:

__interrupt void sciaRXISR(void)
{
    //ESTOP0;

    uint16_t i;

    for(i = 0U; i < 100 ; i++)
    {
        FifoFromWlanUart[FifoFromWlanUartWritePointer] = (uint16_t)
                   (HWREGH(SCIA_BASE + SCI_O_RXBUF) & SCI_RXBUF_SAR_M);
        delay(30000);
        
        if(++FifoFromWlanUartWritePointer>=FifoFromWlanUartLength)
            FifoFromWlanUartWritePointer=0;
        if((FifoFromWlanUart[i-3] == 0x4F && FifoFromWlanUart[i-2] == 0x4B && FifoFromWlanUart[i-1] == 0xD && FifoFromWlanUart[i] == 0xA) ||
                (FifoFromWlanUart[i-6] == 0x45 && FifoFromWlanUart[i-5] == 0x52 && FifoFromWlanUart[i-4] == 0x52 && FifoFromWlanUart[i-3] == 0x4F &&
                        FifoFromWlanUart[i-2] == 0x52 && FifoFromWlanUart[i-1] == 0xD && FifoFromWlanUart[i] == 0xA))
        {
            break;
        }
     }


    SCI_clearOverflowStatus(SCIA_BASE);
    SCI_clearInterruptStatus(mySCIA_BASE, SCI_INT_RXFF);
    //SCI_clearInterruptStatus(mySCIA_BASE, SCI_INT_RXRDY_BRKDT);
    
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9);
}

So my question is, How can I read the complete response without the overflow problem? Solutions and suggestions regarding a way to be able to read the complete responses from the Wifi module without the FiFo overflow would be really helpful. I am stuck at this problem for sometime now and would really apprecite any help. Thank you!!

  • Hi,

    Thanks for your question! So looking at the snippet of code, I have some questions and some potential solutions:

    1. What interrupts do you have enabled? Is this FIFO interrupt, and if so, at what FIFO level is the interrupt configured to fire?

    2. The delay(30000); call seems to likely be erroneous. When you enter the interrupt, you want to empty out the whole FIFO as quickly as possible (because there should be words already in the FIFO). So delaying the reads would actually be problematic in this example.

    3. The loop iteration of 100 times should actually not be possible in a single interrupt. Since the max FIFO depth is 16, only 16 words should need to be read from the FIFO at any time. This leads me to #4 below.

    4. I would re-structure the interrupt to only handle the moving of 16 FIFO characters to memory. Then have a function in the main to periodically check the length of that memory array to see if you've reached your expected number of characters. This will completely avoid any overflow scenario since the interrupt will only be handling the moving of bytes out of the FIFO. It will leave the interrupt reaction time as very fast.

    Let me know if these suggestions help with the issues you are seeing!

    Regards,

    Vince

  • Hi Vince,

    Thank you for the response.

    1. What interrupts do you have enabled? Is this FIFO interrupt, and if so, at what FIFO level is the interrupt configured to fire?

    I am using Tx and Rx FIFO interrupts as mentioned in my question. The Rx FIFO = 6 and Tx FIFO = 16. 

    2. The delay(30000); call seems to likely be erroneous. When you enter the interrupt, you want to empty out the whole FIFO as quickly as possible (because there should be words already in the FIFO). So delaying the reads would actually be problematic in this example.

    I have deleted my delay.

    3. The loop iteration of 100 times should actually not be possible in a single interrupt. Since the max FIFO depth is 16, only 16 words should need to be read from the FIFO at any time. This leads me to #4 below.

    4. I would re-structure the interrupt to only handle the moving of 16 FIFO characters to memory. Then have a function in the main to periodically check the length of that memory array to see if you've reached your expected number of characters. This will completely avoid any overflow scenario since the interrupt will only be handling the moving of bytes out of the FIFO. It will leave the interrupt reaction time as very fast.

    Even when I tried to move only the 16 characters to memory at once, its not working. I can still have only the last 16 characters of the response with the overflow. The thing here is, I do not know the actual length of the response characters to check as you have suggested.

    Is there a way I could send you my code file, so that you can have a correct idea of my code. I am not allowed to attach my code here for certain reasons. 

  • Hi Rashi,

    We try not to debug large amounts code in the forums due to support difficulties that arise form unique use-cases, so I will instead provide a likely solution to your issue:

    Given your RX FIFO depth of 6, we need to change the ISR code as follows (this is identical to the "sci_ex2_loopback_interrupts.c" example from C2000Ware, but modified for a FIFO depth of 6):

    //
    // sciaRXFIFOISR - SCIA Receive FIFO ISR
    //
    __interrupt void sciaRXFIFOISR(void)
    {
        uint16_t i;
    
        SCI_readCharArray(SCIA_BASE, rDataA, 6);
    
        //
        // Check received data
        //
        for(i = 0; i < 6; i++)
        {
            // do what you need to do with the data here
            // move to memory as needed, and handle that
            // memory in the main function
        }
    
        // additional cleanup can go here
        
        
        // now clear the interrupt and return
    
        SCI_clearOverflowStatus(SCIA_BASE);
    
        SCI_clearInterruptStatus(SCIA_BASE, SCI_INT_RXFF);
    
        //
        // Issue PIE ack
        //
        Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9);
    }

    If this does not solve your issue, then please revert back to the "sci_ex2_loopback_interrupts.c" example from C2000Ware and see if that works by default. If it does not, there is a large issue that must be addressed (potentially hardware, or somewhere else in the software system).

    This guide I wrote on debugging such issues may help with this:

    https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1031947/faq-my-c2000-sci-is-not-transmitting-and-or-receiving-data-correctly-how-do-i-fix-this

    Regards,

    Vince