Hi,
I have already studied section 3 (Reset for CPU1 and CPU2) and section 41.2 (Reset for CM) of the TRM. However, several things are still unclear to me. So, I have several questions regarding soft reset for all CPUs.
1- Based on the information in these two sections, we can infer that every resets on the CPU1 yields a reset on the CPU2 and CM, am I right? If so, is there any way to do a soft reset for the CPU1 without resulting in any reset on the other CPUs?
2- Is there an option to do a reset on the CPU2 like "Simulate CPU1 Reset" which is for CPU1? Is it just a specific reset option for only CPU1?
3- What is the best way to use of reset options mentioned in these two sections to separately do a soft reset for all three cores?
4- In the section "3.3.5 Debugger Reset (SYSRS)" of the TRM, it has been mentioned that "Debugger Reset (SYSRS)" (for the CPU2) resets only CPU2, its peripherals, and its clock gating and LPM configuration. First, what is exactly the "LPM configuration" here? Second, what parts of the CPU2 subsystem remain unchanged during this type of reset?
5- On page 161 of the TRM, it has been mentioned that System resets (like SIMRESET.CPU1RSn for the CPU1) reset a large subset of the device but maintain some system-level configuration. What is exactly the "system-level configuration"?
6- In the section "41.2.2 System Reset Request (CMSYSRESETREQ)", it has been mentioned that "This action resets almost all the logic on the CM except for debug". What does it mean by "almost all the logic" and "debug" in this sentence? What parts of the CM subsystem exactly remain unchanged during this type of reset?
7- During the options mentioned to do soft resets in these two sections of the TRM, are RAMs (LSRAMs, GSRAMs, MessageRAMs, and other types of RAMs) remain unchanged? Or will they also be reset?
Best,
Alex