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LAUNCHXL-F28379D: SPI FIFO mode

Part Number: LAUNCHXL-F28379D

void initSPIFIFO()
{
    //
    // Must put SPI into reset before configuring it
    //
    SPI_disableModule(SPIA_BASE);

    //
    // SPI configuration. Use a 500kHz SPICLK and 16-bit word size.
    //
    SPI_setConfig(SPIA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0,
                  SPI_MODE_MASTER, 500000, 16);
    SPI_enableLoopback(SPIA_BASE);
    SPI_setEmulationMode(SPIA_BASE, SPI_EMULATION_STOP_AFTER_TRANSMIT);

    //
    // FIFO and interrupt configuration
    //
    SPI_enableFIFO(SPIA_BASE);
    SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
    SPI_setFIFOInterruptLevel(SPIA_BASE, SPI_FIFO_TX2, SPI_FIFO_RX2);
    SPI_enableInterrupt(SPIA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);

    //
    // Configuration complete. Enable the module.
    //
    SPI_enableModule(SPIA_BASE);
}

//
// SPI A Transmit FIFO ISR
//
__interrupt void spiTxFIFOISR(void)
{
    uint16_t i;
    //
    // Send data
    //
    for(i = 0; i < 16; i++)
    {
       SPI_writeDataNonBlocking(SPIA_BASE, sData[i]);
    }
    //
    // Clear interrupt flag and issue ACK
    //
    SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_TXFF);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
}

//
// SPI A Receive FIFO ISR
//
 __interrupt void spiRxFIFOISR(void)
{
    uint16_t i;

    for(i = 0; i < 16; i++)
    {
        rData[i] = SPI_readDataNonBlocking(SPIA_BASE);
    }

    SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_RXFF);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
}
 __interrupt void adcisr(void)
 {
     static uint16_t p;
     sData[p]=ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER0); //adc result stored in adcres variable
     p++;
     if(p==16)
     {
         p=0;
     }

     ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);//interrupt flag is cleared
     Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1); //to clear any interrupt flag within PIE group
 }

I have tried one exercise in which I want to store ADC result in one array having a size of 16, after 16 ISR that array will be filled and then I want to send that using SPI (FIFO level of 16 defined) and that data need to be stored in another array having SIZE of 16 at receiving end 

Is this code (SPI initialization and ISR shown) do the same things or not?

Regards,
Jay

ss

  • Hi,

    You would receive an SPI ISR whenever Tx FIFO is available for new transfer, This may not ensure you have enough data, in the sData array.

    Why don't you call the SPI_writeData function in the ADC ISR itself?

    Regards.

    Veena

  • yeah, actually I am confused about how transmit/receiving takes place in FIFO mode

    it would be great if you can throw some light on,

    1)Transmit/receiving sequence of operation when FIFO full level=16 (basic info on how operation carried out in steps) 

    2)when transmit FIFO ISR will execute?

    Regards,
    Jay

  • Hi Jay,

    Have you checked the SPI chapter in the device TRM? It provides details regarding SPI FIFO and interrupts.

    In FIFO mode, you can configure when the interrupt needs to be generated.

    Regards,

    Veena

  • Yeah, I have gone through the SPI chapter. but could not understand how TX FIFO status changes
    In TX ISR As I am sending the data by using SPI_writeDataNonBlocking, I can see that as one data sent, RX FIFO status increased by one so I can visualize what is happening at receiving side and as I have kept RX FIFO level 16, as FIFO status>= 16 RX interrupt will occur

    That kind of thing I am not able to visualize at the transmission side.

    Regards,
    Jay

  • Hi Jay,

    The concept is the same on the TX side as well. The status shows how many words are available in the TX FIFO. You may not see that reflecting that on the status register because, the moment you write to FIFO, the SPI module begins transmission and the status will go back to 0 words pending. You could try this on the slave side where Tx does not happen immediately after writing to the Tx FIFO. The slave waits for the clock signal from the master.

    On the interrupt generation side -> On the TX side, you would get an interrupt when there 'N' or lesser words available in FIFO. On the Rx side, you would get an interrupt when there are 'N' or more words available in the FIFO. 'N' is configurable on both Tx and Rx sides separately.

    Regards,

    Veena