TMS320F28388D: Resetting CM core

Hi,

This is part of Cortex-M4 register set and detail can be found in ARM user manual -

Regards,

Vivek Singh

Vivek,

Thanks for the input but I see that CM Core is not getting reset when I perform below operation:

I assume that if I keep breakpoint in main it has to hit that break point after I reset. Correct ?

I tried reading *lRegVal in expressions, it is updating with the expected value of 0x05FA0004.

Als I tried using "SysCtl_simulateReset(SYSCTL_CAUSE_CPU1RSN);" so that all the other CPUs will also reset, but I see that CPU are held in reset and coming up:

Do we have any Library APIs for resetting CPU1 &CPU2 &CM cores independently ? Can you provide us some insights regarding this.

--Pranay.

Hi,

pranay r said:

I assume that if I keep breakpoint in main it has to hit that break point after I reset. Correct ?

Well that depends on how the boot settings are there. Best thing is to check some CPU register or keep the breakpoint at reset vector.

pranay r said:

Als I tried using "SysCtl_simulateReset(SYSCTL_CAUSE_CPU1RSN);" so that all the other CPUs will also reset, but I see that CPU are held in reset and coming up:

CPU1 reset will reset all other cores because the reset configuration bits get reset. User SW need to release both CPU2 and CM out of reset. That is why it is showing CM is held in reset.

pranay r said:

Do we have any Library APIs for resetting CPU1 &CPU2 &CM cores independently ? Can you provide us some insights regarding this.

CPU1 can not be reset independently because it's primary CPU so it reset other cores as well. CPU2 and CM can be reset independently. There are driverlib function SysCtl_controlCMReset and SysCtl_controlCPU2Reset to reset CM and CPU2 from CPU1 code.

Regards,

Vivek Singh

Hi Vivek,

Thanks for the response.

Vivek Singh said:

Well that depends on how the boot settings are there

- How to check this? where to find in code ?

Vivek Singh said:

keep the breakpoint at reset vector

- where to find the reset vector for CPU1/CPU2? Are you referring to the on ein startup_css.c file with name "vectorTableFlash" ?

Vivek Singh said:

User SW need to release both CPU2 and CM out of reset. That is why it is showing CM is held in reset.

I'm only able to perform reset of CPU1/CM/CPU2 using "SysCtl_resetDevice();" with all other commands I'm unable to see a reset happening (atleast I dont know where and what to check)- Tried keeping breakpoint at main but that it isn't helping.

So after performing CPU1 reset if CPU1 boots and main function also executes Device_bootCM(BOOTMODE_BOOT_TO_FLASH_SECTOR0) which releases CM also correct ? But here main itself is not triggering. Please Correct me If my understanding is wrong, or where do I need to release CM and CPU2 out of reset when I reset CPU1 ? I mean where the CPU1 code haults or starts next when resetted.

Vivek Singh said:

driverlib function SysCtl_controlCMReset and SysCtl_controlCPU2Reset to reset CM and CPU2 from CPU1 code

- I Tried using these but dont know how to make sure that CM is booting when I execute these. Please provide some inputs.

Thanks in advance,

Pranay

Hi,

pranay r said:

- How to check this? where to find in code ?

With CCS connected, CPU boot as per EMULATION BOOT and if that is not set correctly then after reset it'll not jump to application. Please check device TRM for more detail about EMULATION BOOT.

pranay r said:

- where to find the reset vector for CPU1/CPU2? Are you referring to the on ein startup_css.c file with name "vectorTableFlash" ?

When you issue reset from CCS (debugger) the PC points to reset vector. Put a breakpoint there.

pranay r said:

So after performing CPU1 reset if CPU1 boots and main function also executes Device_bootCM(BOOTMODE_BOOT_TO_FLASH_SECTOR0) which releases CM also correct ?

That is correct. Please check the emulation boot setting and once you correct that, it should be able to jump to main after reset.

Regards,

Vivek Singh

Hi Vivek,

So I need to perform required settings before resetting the core ? or any other way ?

And As of now I;m using Debug mode so EMUBOOTCONFIG shall be used, but to use in non debug mode ie., for field FW updates can I use FLASH BOOT as our plan is to flash the FW of CPU1 over IPC data received from CM over TCP. Please suggest us any other approach that you came through in any other cases.

Also Do we have any APIs available for configuring

EMUBOOTPINCONFIG , EMUBOOTDEF_LOW/HIGH and EMU_BOOTPIN_CONFIG_KEY registers or Do we need to write explicitly in our FW application ? Can you please suggest APIs if available ?

Thanks,
Pranay

pranay r said:

So I need to perform required settings before resetting the core ? or any other way ?

You have to set it before running the core after reset. So you can set it before reset or after reset but before clicking on run.

pranay r said:

And As of now I;m using Debug mode so EMUBOOTCONFIG shall be used, but to use in non debug mode ie., for field FW updates can I use FLASH BOOT as our plan is to flash the FW of CPU1 over IPC data received from CM over TCP. Please suggest us any other approach that you came through in any other cases.

Yes, EMUBOOT is only applicable with debugger connected. In standalone mode it's don't care so you don't have to use it.

pranay r said:

Also Do we have any APIs available for configuring

As mentioned in last point, EMUBOOT is only for debug so there is no API for this. You need to set it via debugger memory view. There is some predefined Gel command which you can use from CCS menu -

Regards,

Vivek Singh

Hi Vivek,

Thanks for your inputs,

I'm able to reset CPU1 core now.

Vivek Singh said:

Yes, EMUBOOT is only applicable with debugger connected. In standalone mode it's don't care so you don't have to use it.

So you mean that in stand alone mode we need set specific Z1/Z2-BOOTPINCONFIG registers and configure boot table before setting resetting CPU1 right ? Correct me otherwise .

Also How Do I reset CM core ? I tried initiating SysCtl_controlCMReset(SYSCTL_CORE_ACTIVE); from CPU1, In debugger   I see that CM is going into suspended state but still it seems like it is running and when I pause it is says suspended, Ethernet connection no longer works. So I assume that CM went to reset state. So now to boot it, Do I need to explicitly initialize CM core again from CPU1 bu using  Device_bootCM() ?

Please suggest us any better approaches if any.

Also How to use Hex utility for CM core ? for bootloader functionality over TCP.

I'm using "${CG_TOOL_HEX}" "${BuildArtifactFileName}"  -a -o "${BuildArtifactFileBaseName}.txt" - is this enough or any other parameters are required ?

--Pranay

pranay r said:

So you mean that in stand alone mode we need set specific Z1/Z2-BOOTPINCONFIG registers and configure boot table before setting resetting CPU1 right ? Correct me otherwise .

User need to update Z1/Z2-BOOTPINCONFIG if they want to change default boot mode setting else in standalone mode device will boot as per default boot pin value. E.g. if GPIO72/GPIO84 value is driven 1/1 then after reset it'll boot from flash.

pranay r said:

Also How Do I reset CM core ? I tried initiating SysCtl_controlCMReset(SYSCTL_CORE_ACTIVE); from CPU1, In debugger   I see that CM is going into suspended state but still it seems like it is running and when I pause it is says suspended, Ethernet connection no longer works. So I assume that CM went to reset state. So now to boot it, Do I need to explicitly initialize CM core again from CPU1 bu using  Device_bootCM() ?

Yes, after reset, CPU1 application code need to boot the CM as per the need.

pranay r said:

Also How to use Hex utility for CM core ? for bootloader functionality over TCP.

I'm using "${CG_TOOL_HEX}" "${BuildArtifactFileName}"  -a -o "${BuildArtifactFileBaseName}.txt" - is this enough or any other parameters are required ?

I'll have to refer this to other experts in our team.

Regards,

Vivek Singh

Pranay,

Please see below taken from https://www.ti.com/lit/sprabv4 

Thanks and regards,
Vamsi

Hi Vivek,

Vivek Singh said:

User need to update Z1/Z2-BOOTPINCONFIG if they want to change default boot mode setting else in standalone mode device will boot as per default boot pin value. E.g. if GPIO72/GPIO84 value is driven 1/1 then after reset it'll boot from flash.

I want to run in standalone mode and reset CPU1 when received an API and GPIO72/GPIO84 is set to 1/1.
In main FW Application linker file -    I declared BEGIN : origin = 0x084000, length = 0x000002, and in
Custom boot loader I declared as  BEGIN : origin = 0x080000, length = 0x000002, So that when field FW update is required and reset happens SSBL shall boot and wait for FW APIs to be received over IPC.

So Now for my above requirement, Only setting GPIO72/84 as 1/1 is enough right ? or Do I need to do anything explicitly ie., writing into any Config registers or so ?

--Pranay.

Hi Pranay,

pranay r said:

In main FW Application linker file -    I declared BEGIN : origin = 0x084000, length = 0x000002, and in
Custom boot loader I declared as  BEGIN : origin = 0x080000, length = 0x000002, So that when field FW update is required and reset happens SSBL shall boot and wait for FW APIs to be received over IPC.

So Now for my above requirement, Only setting GPIO72/84 as 1/1 is enough right ? or Do I need to do anything explicitly ie., writing into any Config registers or so ?

We have only below entry point option when booting from flash -

If your idea is to boot from different address after reset then it has to be one of these address but please note that once you change this configuration then it'll always boot from that location and your SSBL will not run again. In this case my suggestion will be to have some intelligence built in SSBL to know if it need to program the FW or directly jump to FW. So after reset SSBL will check if it need to program the FW and if not then it'll jump to entry point of existing FW. Hope this is clear.

Regards,

Vivek Singh  

Hi vivek, yes correct 

our logic in Ssbl will be polling for particular memory in flash and validate whether a keyword is met or not if met it will boot to FW else it will be in program mode till we update that particular location with required keyword. 

From the above screenshot,You mean to say that we can’t boot from sector 3 ? I’m using lb assembly command for branching to respective FW flash sector. Will it not work ?

pranay r said:

From the above screenshot,You mean to say that we can’t boot from sector 3 ? I’m using lb assembly command for branching to respective FW flash sector. Will it not work ?

You can branch to anywhere in flash from your SSBL. The entry point mentioned in table are default entry point where CPU will start executing exiting from TI ROM code. 

Regards,

Vivek Singh

Right.

So Now for my above requirement, Only setting GPIO72/84 as 1/1 is enough right ? or Do I need to do anything explicitly ie., writing into any Config registers or so ?

Thanks vivek for the confirmation.

And I'm facing another issue here,

In CPU1 when we receive an API I will be resetting CM Core using "SysCtl_controlCMReset(SYSCTL_CORE_ACTIVE);"

and will Start a timer in CPU1 and in expiry I'm calling below functions:

I see that CM core is getting resetted and restarted from main() as expected but in main() of CM core when we call

"IPC_registerInterrupt(IPC_CM_L_CPU1_R, IPC_INT0, IPC_ISR0);", It is going into FaultISR() loop.And I'm stuck with this debug since past 2 days trying to figure out what is going wrong.

can you please help me out here.

Thanks and regards,

Pranay

Pranay,

Did you check the Fault status in CM (CFSR register - 0xE000ED28) to know what has caused the fault ? 

Vivek Singh

Hi VIvek,

I'm seeing below data in CFSR register:

I further tried digging the root cause and found this;

I see that Bus fault address register :

next tried searching that address in disassembly but didnt find anything.

--Pranay

Pranay,

Look like some issue with un-initialize pointer. Please check for that in your code. 

Regards,

Vivek Singh 

Hi Pranay, 

Since other issues are getting discussed in different E2E posts, can we close this one ? 

Regards,

Vivek Singh