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TMS320F28388D: ADC design without unity gain buffer op amp

Sainath Drasha
Prodigy 10 points
Part Number: TMS320F28388D
Other Parts Discussed in Thread: PSPICE-FOR-TI, TINA-TI

Hello,

I am trying to design ADC circuit for the specified part number. I need a sample rate of 100 KSPS to measure the input voltage range of 0 to 30 V. The input voltage is fed to the ADC after a resistor divider. As I understand I will have to implement buffer and RC filter between the divider and the ADC to isolate the high impedance of the divider. I would like to know for the given sample rate, how much resistance/ impedance can I use so I can avoid using the buffer op amp. Is it possible or buffer has to be included?

  • 0
    TI__Guru 60865 points

    Hi Sainath,

    See this app. note: https://www.ti.com/lit/an/spracv0/spracv0.pdf

    I do think that you will probably need a buffer for 100ksps sampling. You might be able to get away with using a low-cost op-amp (with say a couple 100 kHz BW) to decouple the voltage divider from the ADC while still using charge-sharing with a very small resistor value.  (This would be as opposed to using a high-speed driving op-amp with several MHz bandwidth, see https://www.ti.com/lit/an/spract6/spract6.pdf for the design flow for this type of driver if necessary).

  • 0 in reply to Devin Cottier
    Prodigy 10 points

    Hi Devin,

    Thank you for writing me. I have read the pdf that you have shared, very helpful. but I still want to know If I want to absolutely avoid the buffer, is there a method that I can adopt ?

    I have noticed that a similar information on the thread: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/830878/tms320f280049-fast-adc-inputs-what-is-the-use-of-op-amp-as-buffer-in-between

    Here you write, "if the impedance becomes too high, the circuit will probably have issues settling". This interests me, and I want to know, what do you mean by very high impedance? what's the limit? in terms of ohms or kohms..? I want to choose a low impedance divider but how do I decide if the impedance is low or high?  

  • +1 in reply to Sainath Drasha
    TI__Guru 60865 points

    Hi Sainath,

    For high-speed ADC drivers, there is a tradeoff of driving impedance vs. settling speed.  For a given settling speed, you can then further trade off S+H time vs settling error (generally you want to use the full settling time for 1/2 LSBs unless your application can accept lower resolution).  The best way to explore this trade-off is to simulate your circuit in TINA-TI (or PSPICE-for-TI) per SPRACT6 document linked above.  The TRMs of each device also have a  "choosing an acquisition window duration" section that will help you estimate the settling error analytically.

    For charge-sharing ADC drivers, there is a tradeoff of sample rate vs. tracking error for a given impedance.  The capacitance size can also be modulated if you can accept additional error (for applications that can accept lower resolution). By far the best way to explore these tradeoffs is to simulate using TINA-TI (or PSPICE-for-TI) using the app. note SPACV0 linked above.  The app. note also has some analytical formulas you can use: 

    F28388D has a 14.5pF S+H capacitor, so 14.5*2^(12+2) = 238nF.  Therefore

    Rs <= 1/(0.7*100ksps*238nF) => Rs <= 60 ohms      

    60 ohms is probably not practical for a voltage divider, but you can probably get a cheap op-amp with >400kHz BW that can drive 238nF through 60 ohms and remain stable.