Part Number: TMS320F28374D
Hello TI support,
I have read the discussion you can find at this thread
since I'm facing with a similar issue. Please let me describe my scenario.
I'm developing a digital control with TI-F28374D where all ePWM units (12 ePWM modules ) are involved into switching action of the power converter. For each ePWM unit, its output signals EPWMxA and EPWMxB run into complementary way, and the 12 ePWM units are interleaved over one switching period.
That are some strong constraints for my application: all timer belonging to the ePWM modulator run up-down at the same frequency, and I have to perform oversampling over one switching period. The rate is 8, meaning that over one switching period the ADC module starts 8 times; further for each "ADC start event" over one switching period, all 16 ADC input channels are sampled.
I have decided to use CPU1 Timer1 to start the 16 SOCs, every times CPU1 Timer1 counter gets underflow, and the time period isTAdcSoc:
Over sampling factor = 8
Tpwm = swiching period
TAdcSoc = Tpwm / 8
and according to the ADC Soc trigger as shown below.
Here the setting
Then, the end of conversion of the ADC, triggers a CLA task that reads ADC result registers and makes calculation.
That's my scenario.
Now, let me approach my doubts.
According to the synchronization scheme,
I can not put the Cpu1 Timer1 on the synchronization chain of the ePWM module, and that make me worried about a potential time shift among CPU1 Timer1 and EPWM1 unit which I set as master of the synch chain.
The discussion at the mentioned thread suggests to use software to perform synchronization among ePWM module and CPU1 Timer1, with a tradeoff among the accuracy.
Here my question: is what the mentioned thread states still valid or you have a new tip to suggest ?
From my point of view, CPU1 Timer1 should have a synchronization input from synch chain, since the ADC module is always related to the ePWM module. With the current design of the chip, CPU1 Timer1 and ePWM module are indipendent over the time and that sounds strange However, to be honest I have run out the chip resources.
Anyway, let me propose an idea to overcome the missing synch feature.
The CLA task at the end of the oversamping period, I mean 1 times over 8 "SOC ADC event", could notify to the CPU an interrupt, for instance interrupt number 1 of the eleventh group.
The Cpu1 serves the interrupt request, and here stops CPU1 Timer1. Anything else.
Due to the design of the interleaving architecture over one switching period of the under discussion interrupt, CPU1Timer1 is being stopped till the beginning of the next control interrupt running at Tpwm period.
Referring to the next picture
Green trace = Epwm1 interrupt
Red trace up down = Epwm1 counter
Red trace down = Cpu1 Timer1 counter
Blue trace = Cla1 task1
We can see that Cla1 task1 is called 8 times over one switching period, Tpwm.
We can see that the period of CPU1 Timer1 is Tpwm/8 since the over sampling factor is 8
Yellow trace = CPU1 serves interrupt requested by latest CLA1 Task, the 8th, and stops the CPU1 Timer1.
Referring to the green circle on the next picture, the next Epwm1 interrupt will start again CPU1 Timer1, and that makes the synch process feasible.
That's my proposal to overcome the missing synch feature.
Please, what do you think about ?
Best regards,
Ettore
