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TMS320F28388D: The T-format encoder code stays at PM_tformat_startOperation

Part Number: TMS320F28388D
Other Parts Discussed in Thread: SYSCONFIG

Hi experts,

When I used the control board(Chip: F28388D) designed by myself to do the experiment about the encoder, the T-format encoder code stays at PM_tformat_startOperation,and unable to obtain rotor position information.On the one hand, I have been able to get Txen,SOMI and CLKS waveforms (The clock has a frequency of 2.5MHZ)as shown below:

On the other hand, the code stays in the PM_tformat_startOperation () function, as shown below:

Above question, hope can get expert's guidance, thanks!

Best regards

Johnson Alanl

  • I would start by checking the power to the encoder.  If you can power it separately but with a common ground. 

  • Thank you very much for your reply! In fact, I have provided the encoder with a stable separate power supply, and with a common ground.In addition, data from the encoder can also be measured. But the code stays in the PM_tformat_startOperation () function.

  • Great!

    The CLB generates the SPI clock - is this output from the CLB routed back into the SPI?  

  • The CLB generates the SPI clock - is this output from the CLB routed back into the SPI?  

    The clock generated by CLB is routed to the SPI module through the PWM4B port,Configurations of GPIO ports are as follows:

    void tformat_setupGPIO(void)
    {
    
        //
        // GPIO7 is SPI Clk slave
        //
        GPIO_setMasterCore(7, GPIO_CORE_CPU1);
        GPIO_setPinConfig(GPIO_7_EPWM4B);
    
        //
        // GPIO16 is the SPISIMOA
        //
        GPIO_setMasterCore(16, GPIO_CORE_CPU1);
        GPIO_setPinConfig(GPIO_16_SPIA_SIMO);
        GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC);
    
        //
        // GPIO17 is the SPISOMIA
        //
        GPIO_setMasterCore(17, GPIO_CORE_CPU1);
        GPIO_setPinConfig(GPIO_17_SPIA_SOMI);
        GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC);
    
        //
        // GPIO18 is the SPICLKA
        //
        GPIO_setMasterCore(18, GPIO_CORE_CPU1);
        GPIO_setPinConfig(GPIO_18_SPIA_CLK);
        GPIO_setQualificationMode(18, GPIO_QUAL_ASYNC);
    
        //
        // GPIO19 is the SPISTEA
        //
        GPIO_setMasterCore(19, GPIO_CORE_CPU1);
        GPIO_setPinConfig(GPIO_19_SPIA_STEN);
        GPIO_setQualificationMode(19, GPIO_QUAL_ASYNC);
    
    
        //
        // GPIO15 is tformat TxEN
        //
        GPIO_setMasterCore(15, GPIO_CORE_CPU1);
        GPIO_setPinConfig(GPIO_15_OUTPUTXBAR4);
    
    }

    I can capture the clock waveform at the clock output port PWM4B (GPIO7) and GPIO18, which indicates that the SPI module can get the clock normally.

  • Lori,

    I built a new CCS project from scratch,I directly use the probe of the logic analyzer to measure the pin of the chip (F28388D), which can measure the clock waveform, enable waveform, instructions issued by MCU, as well as the data feedback from the encoder.These all show that my MCU works well.And now the code stays in while(tformatData.dataready!= 1);/ / {}

    I tried to make the encoder use a separate power and carefully common ground, but unfortunately couldn't solve the problem.

    Best regards

    Johnson Alanl

  • Was the project working before?  You mentioned this is a board you designed.  If the project works on another board then I suspect something in the hardware.  

    If I understand:

    • The clock from CLB to SPI has been checked at both points (the pin where the CLB outputs on ePWM and the SPI input). 
    • The clock is the right frequency (2.5 MHz)
    • The message request goes out from the C28x. 
    • The encoder responds, but the C28x doesn't see the response.  In your first screenshot - does the clock continue toggling?  It stops so it looks like the CLB itself is not seeing the incoming response. When the first falling edge comes in on SIMO, the CLB should start clocking the SPI.   It should come through an input XBAR from the SIMO to the CLB. 
  • The encoder responds, but the C28x doesn't see the response.  In your first screenshot - does the clock continue toggling?  It stops so it looks like the CLB itself is not seeing the incoming response. When the first falling edge comes in on SIMO, the CLB should start clocking the SPI.   It should come through an input XBAR from the SIMO to the CLB. 

    This does look like an encoder response, but C28x does not see the response.So where else do I need to change the code besides the following?

    Best regards

    Johnson Alanl

  • Lori,

    Thank you very much for your reply!I think I've found the key to solving the problem, in my code I'm using the clock waveform from the PWM4 port, so I might not be able to use SPIA.Because I saw this table in the chip manual:

    Please check if this means CLB4 must be used if using PWM4 port to generate waveform and then must be bound to SPID module as well.

    Best regards

    Johnson Alanl

  • Johnson,

    Yes, only certain CLB tiles can output on specific peripherals.  In this example CLB4 can override ePWM4 output.

    On TI's boosterpack (https://www.ti.com/tool/BOOSTXL-POSMGR) hardware the connection from the ePWM4 pin and the SPICLK is made externally to the device.   

    The thing is - if the message to the encoder is going out, then the SPI is getting clocked. Otherwise the message would not go out.  I suspect the response to the SPI is not going to the right place or the CLB does not see it.  The CLB will only re-start the SPI clock once it sees the first falling edge of the response.  To summarize -  The response should go to both the SPI (SPISMOB) and to the CLB. 

    Regards

    Lori

  • I suspect the response to the SPI is not going to the right place or the CLB does not see it. 

    Lori,How do I check for these?

    Best regards

    Johnson Alanl

  • Lori,

    I have changed PWM4 to PWM1, CLB4 to CLB1, and got data on SIMO pins (as shown below), but unfortunately the code still stops at: while(tformatData.dataready!= 1);/ / {}

    1. In addition, I would like to ask whether the logical configuration in the CLB system file needs to be modified, as shown below:

    2.Could you please help to check the rationality of the hardware design?

    Best regards

    Johnson Alanl

  • Johnson,

    Was the project working before on 2838x?  If the project works on another board then I suspect something in the hardware.  I thought based on some of our other discussions the SW was working before?

    1. In addition, I would like to ask whether the logical configuration in the CLB system file needs to be modified, as shown below:

    If moving between tiles, then the mux to input to and output from the CLB may need to be changed. 

    For example - the MUX signal chain for the SPI data incoming to the CLB will need to be changed to CLB tile1. The input is likely coming through the INPUTXBAR to the CLB AUX signals then into the CLB tile.  In this case the tile # would need to change. 

    Another example, as you mention, CLB1 can override ePWM1 output pins directly, but not other pins associated with ePWM2, 3 etc.  So you had to change the ePWM instance.

    Something that has helped me a TON working out the signal-chain in and out is our SysConfig tool.  The latest versions of SysConfig have support for the CLB MUX and the INPUT/OUTPUT XBARS.  You may find it helpful.   Unfortunately the existing t-format project hasn't been migrated to SysConfig yet, but you may find it helpful for your project. 

    2.Could you please help to check the rationality of the hardware design?

    I can look at it closer next week, but all I will be doing is comparing it with our reference design schematics: 

    https://www.ti.com/tool/BOOSTXL-POSMGR

    Design files: https://www.ti.com/lit/zip/sprr422

    Best regards

    Lori

    Best regards

    Lori

  • Lori,Thank you very much for your last reply.

    I checked the hardware circuits again, but I didn't find anything wrong.However, I found that no matter how I rotated the encoder axis, SPI related parameters in the register did not change. Does this mean that although I had measured the data in the pin of the chip (F28388D), these data were not mapped to the register normally?I think maybe I should check the SPI code Settings.

    Best regards

    Johnson Alanl

  • Johnson,

    Yes, check the SPI configuration.  Double check that the SPI being used in the design is the same as your board.  Check the SPI settings but also the interrupt configuration matches the right SPI module. I believe the code, as supplied, is setup for SPI-B. 

    Also please confirm that my understanding of the issue is correct -

    If I understand:

    • The clock from CLB to SPI has been checked at both points (the pin where the CLB outputs on ePWM and the SPI input). 
    • The clock is the right frequency (2.5 MHz)
    • The message request goes out from the C28x. 
    • The encoder responds, but the C28x doesn't see the response.  In your first screenshot - does the clock continue toggling?  It stops so it looks like the CLB itself is not seeing the incoming response. When the first falling edge comes in on SIMO, the CLB should start clocking the SPI.   It should come through an input XBAR from the SIMO to the CLB.

    I asked one of my hardware colleagues to take a look at the screenshots you sent and compare them to our reference design.  I should hear back from them by the end of the week.

    Regards,

    -Lori 

  • Hi Johnson,

    My colleague took a look at the encoder portion of your design and didn't find anything that looked incorrect. 

    Regards

    Lori

  • Hi Lori,

    Thank you and your colleagues very much for helping me. Thank you again!

    Best regards

    Johnson Alanl

  • Hi,Lori:
    I think I found the reason why the code is stuck in the while loop. By comparing the clock waveform of F280049C (F280049C has been debugged successfully) with that of F28388D,I found that F28388D received data clock number is abnormal (the normal number of received data clock should be slightly more than the number of received data bits), as shown below are F28388D received data clock and F280049C received data clock:

    So, do you think the code stays in the while loop because of this problem?If I am right, how can I modify the code to meet this requirement?

    Best regards

    Johnson Alanl

  • Referring to the T-format guide -  When the falling edge of the response is seen, the HLC should update the match2 value for counter1.  Then FSM1 stays in state 1,1 (Receive Data) until counter1 match2 is reached.

    Did you change any of the logic related to this?  

  • Hi,Lori:

    My encoder has successfully read the data, and I have changed the clock number.Thanks for your guidance!

    Best regards

    Johnson Alanl

  • That's great news!  What was the issue if you don't mind sharing?  I can learn as well. 

    Cheers

    Lori

  • Hi,Lori:

    I carefully compared the CLB parameters and modified it, perhaps because I changed the original algorithm from the beginning.In addition, SPI and CLB also have a one-to-one correspondence, which can not be ignored.

    Best regards

    Johnson Alanl