TMS320F28388D: Interrupt works in C but not in ASM

Hi, 

Thanks Geoffrey. As you said, I add further details below.

Here is the interrupt coded in asm in the source file interrupt_EPwm1_latency_isr:

;******************************************************************************
; FILE: interrupt_EPwm1_latency_isr.asm
;
; DESCRIPTION: EPwm1 Interrupts in assembly
;

; EPwm1 interrupts in assembly. These are tweaked for the shortest possible
; response time. Interrupt toggle GPIO35. These only save a couple cycles vs.
; their C equivalents.
	.global _EPWM1_ISR

	.sect ".TI.ramfunc"

_EPWM1_ISR:
    ASP                   ;Align stack pointer. Real ISRs will probably need this.
    MOVZ DP, #7f00h >> 6  ;Load DP with the GPIO data registers' base address (0x7f00)
    MOV @ah, #0008h       ;Set bit 3 of GPBSET (address 0x7f0a)
    RPT #190 || NOP		  ;Attente 1 µs
    MOV @0bh, #0008h      ;Set bit 3 of GPBCLEAR (address 0x7f0c)
    MOVZ DP, #4000h >> 6  ;Load DP with the EPWM1 registers' base address (0x4000)
    MOV @0aah, #0001h     ;Set bit 0 of ETCLR (address 0x40aa)
    MOVZ DP, #0cc0h >> 6  ;Load DP with a value close to the PIEACK address (0xcc0).
                          ;We can't use the PIE base address of 0xce0 because the
                          ;0x20 bit gets dropped during the right-shift.
    MOV @21h, #0004h      ;Write to PIEACK to re-enable the interrupt group 3
    NASP                  ;Unalign stack pointer. Again, this is only here for realism.
    IRET

	.end
;//===========================================================================
;// End of file.
;//===========================================================================

When I run the code in debug mode, it's not passing throw the interrupt.

Here is the interrupt coded in C in the source file f2838x_defaultisr:

//
// 3.1 - ePWM1 Interrupt
//
interrupt void EPWM1_ISR(void)
{
    //
    // Insert ISR Code here
    //
    //GpioDataRegs.GPBTOGGLE.bit.GPIO35 = 1;   // Toggle GPIO35 à chaque passage dans l'interruption
    GpioDataRegs.GPBSET.bit.GPIO35 = 1;   // Set GPIO35 to 1
    asm(" RPT #190 || NOP");              // Equivaut à 1us à une horloge de 190 MHz (validé en pratique)
    GpioDataRegs.GPBCLEAR.bit.GPIO35 = 1;   // Set GPIO35 to 0

    EPwm1Regs.ETCLR.bit.INT = 1;             // Clear ETFLG[INT] flag and enable further interrupts pulses to be generated

    //
    // To receive more interrupts from this PIE group,
    // acknowledge this interrupt.
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

    //
    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    //
    //asm ("      ESTOP0");
    //for(;;);
}

When I run the code in debug mode, it's working properly. It passes through the interrupt and generates a 1µs pulse as wanted here.

And below, you can find source files about the set up of PWM1 interrupt.

/**********************************************************************
* File: Adc.c -- Solution File
* Devices: TMS320F28x8x
* Author: ACR
**********************************************************************/

#include "psu1kWvienna.h"				// Main include file


/**********************************************************************
* Function: InitAdca()
*
* Description: Initializes ADC-A on the F28x7x
**********************************************************************/
void InitAdca(void)
{
	EALLOW;						// Enable EALLOW protected register access

//--- Reset the ADC.  This is good programming practice.
	DevCfgRegs.SOFTPRES13.bit.ADC_A = 1;	// ADC is reset
	DevCfgRegs.SOFTPRES13.bit.ADC_A = 0;	// ADC is released from reset

//--- Configure the ADC base registers
	AdcaRegs.ADCCTL1.all = 0x0004;		// Main ADC configuration
// bit 15-14     00:     reserved
// bit 13        0:      ADCBSY, ADC busy, read-only
// bit 12        0:      reserved
// bit 11-8      0's:    ADCBSYCHN, ADC busy channel, read-only
// bit 7         0:      ADCPWDNZ, ADC power down, 0=powered down, 1=powered up
// bit 6-3       0000:   reserved
// bit 2         1:      INTPULSEPOS, INT pulse generation, 0=start of conversion, 1=end of conversion
// bit 1-0       00:     reserved

	AdcaRegs.ADCCTL2.all = 0x0006;		// ADC clock configuration
// bit 15-8      0's:    reserved
// bit 7         0:      SIGNALMODE, configured by AdcSetMode() below to get calibration correct
// bit 6         0:      RESOLUTION, configured by AdcSetMode() below to get calibration correct
// bit 5-4       00:     reserved
// bit 3-0       0110:   PRESCALE, ADC clock prescaler.  0110=CPUCLK/4=47.5MHz, max datasheet ADCCLK = 50MHz

	AdcaRegs.ADCBURSTCTL.all = 0x0000;
// bit 15        0:      BURSTEN, 0=burst mode disabled, 1=burst mode enabled
// bit 14-12     000:    reserved
// bit 11-8      0000:   BURSTSIZE, 0=1 SOC converted (don't care)
// bit 7-6       00:     reserved
// bit 5-0       000000: BURSTTRIGSEL, 00=software only (don't care)

//--- Call AdcSetMode() to configure the resolution and signal mode.
//    This also performs the correct ADC calibration for the configured mode.
    AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

//--- SOC0 configuration
	AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5;		// Trigger using ePWM1-ADCSOCA
	AdcaRegs.ADCSOC0CTL.bit.CHSEL = 2;			// Convert channel ADCINA2 (Ch. 2)
	AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19;			// Acquisition window set to (19+1)=20 cycles (105.3 ns with 190 MHz SYSCLK)
	                                            // Requirement: min 75ns for 12bit with Rs�rie<50Ohm

	AdcaRegs.ADCINTSOCSEL1.bit.SOC0 = 0;		// No ADC interrupt triggers SOC0 (TRIGSEL field determines trigger)

	AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;	// All SOCs handled in round-robin mode

//--- Set up trigger source for ADC => SOCA
	// Select SOC from counter at CMPB when timer is incrementing
	EPwm1Regs.ETSEL.bit.SOCASEL = 6;            // EPwm1SOCA pulse generated  when counter = CMPB or D when timer is incrementing
	EPwm1Regs.ETSEL.bit.SOCASELCMP = 0;         // Enable event: time-base counter equal to CMPB when the timer is increasing
	EPwm1Regs.CMPB.all = TRIGGER_EPWM1_SOCA;    // Trigger when counter is incrementing and CTR = CMPB

	EPwm1Regs.ETPS.bit.SOCPSSEL = 0;            // SOCAPRD determine frequency of events
	EPwm1Regs.ETPS.bit.SOCAPRD = 1;             // Generate EPWMxSOCA pulse on the first event

	EPwm1Regs.ETSEL.bit.SOCAEN = 0;             // Enable SOCA pulse, disable pour le moment, pas de conversion analogique num�rique

//--- Set up interrupt source EPwm1 at CTR up = CMPB
	EPwm1Regs.ETSEL.bit.INTSELCMP = 0;          // Enable event: time-base counter equal to CMPB when the timer is increasing
	EPwm1Regs.ETSEL.bit.INTSEL = 6;             // Interrupt generated  when counter = CMPB or D when timer is incrementing
	EPwm1Regs.CMPB.bit.CMPB = TRIGGER_EPWM1_SOCA;    // Trigger when counter is incrementing and CTR = CMPB

	EPwm1Regs.ETPS.bit.INTPSSEL = 0;            // INTPRD determine frequency of events
	EPwm1Regs.ETPS.bit.INTPRD = 1;              // Generate interrupt on the first event

	EPwm1Regs.ETSEL.bit.INTEN = 1;              // Enable PWM1x_INT generation

//--- ADCA1 interrupt configuration
	/*AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1;		// Interrupt pulses regardless of flag state
	AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;		// Enable the interrupt in the ADC
	AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0;*/		// EOC0 triggers the interrupt

//--- Enable the ADC interrupt
	/*PieCtrlRegs.PIEIER1.bit.INTx1 = 1;			// Enable ADCA1 interrupt in PIE group 1
	IER |= 0x0001;*/								// Enable INT1 in IER to enable PIE group

//--- Finish up
	AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;			// Power up the ADC
	asm(" RPT #190000 || NOP");					// Wait 1 ms after power-up before using the ADC, power up time max 500us
	EDIS;								        // Disable EALLOW protected register access

} // end InitAdc()


//--- end of file -----------------------------------------------------

/**********************************************************************
* File: EPwm.c -- Solution File
* Devices: TMS320F28x8x
* Author: ACR
**********************************************************************/

#include "psu1kWvienna.h"				// Main include file


/**********************************************************************
* Function: InitEPwm()
*
* Description: Initializes the Enhanced PWM modules on the F28x8x
**********************************************************************/
void InitEPwm(void)
{
    EALLOW;						// Enable EALLOW protected register access

	// Configure the prescaler to the ePWM modules.  Max ePWM input clock is 100 MHz on F2837xD. On the target F2838xD, max ePWM input clock is 200MHz.
	ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;     // EPWMCLK divider from PLLSYSCLK.  0=/1, 1=/2

	// Must disable the clock to the ePWM modules if you want all ePWM modules synchronized.
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

	EDIS;						// Disable EALLOW protected register access

//---------------------------------------------------------------------
//--- Configure ePWM1 for 250 kHz symmetric PWM on EPWM1A pin and Complementary Output on EPWM1B with dead time
//---------------------------------------------------------------------
	EALLOW;							// Enable EALLOW protected register access
	DevCfgRegs.SOFTPRES2.bit.EPWM1 = 1;		// ePWM1 is reset
	DevCfgRegs.SOFTPRES2.bit.EPWM1 = 0;		// ePWM1 is released from reset
	EDIS;							// Disable EALLOW protected register access

	EPwm1Regs.TBCTL.all = 0xC003;			// Configure timer control register

	EPwm1Regs.TBCTR = 0x0000;				// Clear timer counter
	EPwm1Regs.TBPRD = PWM_VIENNA_PERIOD;		// Set timer period, shadowed par d�faut TBCTL[PRDLD]=0
	EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;		// Set timer phase
	EPwm1Regs.CMPA.bit.CMPA = PWM_DUTY_CYCLE_75;	// Set PWM duty cycle

	EPwm1Regs.CMPCTL.all = 0x0000;			// Compare control register, shadow mode for CMPx loading

    //Shadow mode register pour l'Action Qualifier
    EPwm1Regs.AQCTL.bit.SHDWAQAMODE = 1;    // Action Qualifier Operates as a Double Buffer
    EPwm1Regs.AQCTL.bit.LDAQAMODE = 0;      // Load on CTR = 0
    EPwm1Regs.AQCTL.bit.LDAQASYNC = 0;      // Shadow to active load occurs according to LDAQAMODE

	EPwm1Regs.AQCTLA.all = 0x0060;		// Action-qualifier control register A
	EPwm1Regs.AQSFRC.all = 0x0000;		// Action-qualifier s/w force register
	EPwm1Regs.AQCSFRC.bit.CSFA = 1;		// Action-qualifier continuous s/w force register, force EPWM1A to 0, EPWM1B=1 car mode compl�mentaire
	EPwm1Regs.AQCSFRC.bit.CSFB = 0;     // Action-qualifier continuous s/w force register, ignor� en mode compl�mentaire

	EPwm1Regs.PCCTL.bit.CHPEN = 0;		// PWM chopper unit disabled
	EPwm1Regs.TZDCSEL.all = 0x0000;		// All trip zone and DC compare actions disabled

	EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;	// Enable the timer in count up/down mode

	//Configuration de EPWM1B en Active High Complementary Mode
	EPwm1Regs.DBCTL.bit.IN_MODE = 0;    // EPWM1A is the source for both rising-edge and falling-edge delay
	EPwm1Regs.DBCTL.bit.POLSEL = 2;     // Active High Complementary Mode (EPWM1B is inverted)
	EPwm1Regs.DBCTL.bit.OUT_MODE = 3;   // DBM is fully enabled

	//Param�trage des temps morts (ils ne sont pas centr�s)
	EPwm1Regs.DBFED.all = DT_VIENNA_PWM;           // 65ns de temps mort (half cycle d�sactiv�)
	EPwm1Regs.DBRED.all = DT_VIENNA_PWM;           // 65ns de temps mort (half cycle d�sactiv�)


//---------------------------------------------------------------------
//--- Configure ePWM2 for 250 kHz symmetric PWM on EPWM2A pin
//---------------------------------------------------------------------
    EALLOW;                         // Enable EALLOW protected register access
    DevCfgRegs.SOFTPRES2.bit.EPWM2 = 1;     // ePWM2 is reset
    DevCfgRegs.SOFTPRES2.bit.EPWM2 = 0;     // ePWM2 is released from reset
    EDIS;                           // Disable EALLOW protected register access

    EPwm2Regs.TBCTL.all = 0xC003;           // Configure timer control register

    EPwm2Regs.TBCTR = 0x0000;               // Clear timer counter
    EPwm2Regs.TBPRD = PWM_VIENNA_PERIOD;        // Set timer period, shadowed par d�faut TBCTL[PRDLD]=0
    EPwm2Regs.TBPHS.bit.TBPHS = 0x0000;     // Set timer phase
    EPwm2Regs.CMPA.bit.CMPA = PWM_DUTY_CYCLE_50;   // Set PWM duty cycle

    EPwm2Regs.CMPCTL.all = 0x0000;          // Compare control register, shadow mode for CMPx loading

    //Shadow mode register pour l'Action Qualifier
    EPwm2Regs.AQCTL.bit.SHDWAQAMODE = 1;    // Action Qualifier Operates as a Double Buffer
    EPwm2Regs.AQCTL.bit.LDAQAMODE = 0;      // Load on CTR = 0
    EPwm2Regs.AQCTL.bit.LDAQASYNC = 0;      // Shadow to active load occurs according to LDAQAMODE

    EPwm2Regs.AQCTLA.all = 0x0060;      // Action-qualifier control register A
    EPwm2Regs.AQSFRC.all = 0x0000;      // Action-qualifier s/w force register
    EPwm2Regs.AQCSFRC.bit.CSFA = 1;     // Action-qualifier continuous s/w force register, force EPWM2A to 0, EPWM2B=1 car mode compl�mentaire
    EPwm2Regs.AQCSFRC.bit.CSFB = 0;     // Action-qualifier continuous s/w force register, ignor� en mode compl�mentaire

    EPwm2Regs.PCCTL.bit.CHPEN = 0;      // PWM chopper unit disabled
    EPwm2Regs.TZDCSEL.all = 0x0000;     // All trip zone and DC compare actions disabled

    EPwm2Regs.TBCTL.bit.CTRMODE = 0x2;  // Enable the timer in count up/down mode

    //Configuration de EPWM2B en Active High Complementary Mode
    EPwm2Regs.DBCTL.bit.IN_MODE = 0;    // EPWM2A is the source for both rising-edge and falling-edge delay
    EPwm2Regs.DBCTL.bit.POLSEL = 2;     // Active High Complementary Mode (EPWM2B is inverted)
    EPwm2Regs.DBCTL.bit.OUT_MODE = 3;   // DBM is fully enabled

    //Param�trage des temps morts (ils ne sont pas centr�s)
    EPwm2Regs.DBFED.all = DT_VIENNA_PWM;           // 65ns de temps mort (half cycle d�sactiv�)
    EPwm2Regs.DBRED.all = DT_VIENNA_PWM;           // 65ns de temps mort (half cycle d�sactiv�)

//---------------------------------------------------------------------
//--- Configure ePWM3 for 250 kHz symmetric PWM on EPWM3A pin
//---------------------------------------------------------------------
    EALLOW;                         // Enable EALLOW protected register access
    DevCfgRegs.SOFTPRES2.bit.EPWM3 = 1;     // ePWM3 is reset
    DevCfgRegs.SOFTPRES2.bit.EPWM3 = 0;     // ePWM3 is released from reset
    EDIS;                           // Disable EALLOW protected register access

    EPwm3Regs.TBCTL.all = 0xC003;           // Configure timer control register

    EPwm3Regs.TBCTR = 0x0000;               // Clear timer counter
    EPwm3Regs.TBPRD = PWM_VIENNA_PERIOD;        // Set timer period, shadowed par d�faut TBCTL[PRDLD]=0
    EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;     // Set timer phase
    EPwm3Regs.CMPA.bit.CMPA = PWM_DUTY_CYCLE_75;   // Set PWM duty cycle

    EPwm3Regs.CMPCTL.all = 0x0000;          // Compare control register, shadow mode for CMPx loading

    //Shadow mode register pour l'Action Qualifier
    EPwm3Regs.AQCTL.bit.SHDWAQAMODE = 1;    // Action Qualifier Operates as a Double Buffer
    EPwm3Regs.AQCTL.bit.LDAQAMODE = 0;      // Load on CTR = 0
    EPwm3Regs.AQCTL.bit.LDAQASYNC = 0;      // Shadow to active load occurs according to LDAQAMODE

    EPwm3Regs.AQCTLA.all = 0x0060;      // Action-qualifier control register A
    EPwm3Regs.AQSFRC.all = 0x0000;      // Action-qualifier s/w force register
    EPwm3Regs.AQCSFRC.bit.CSFA = 1;     // Action-qualifier continuous s/w force register, force EPWM3A to 0, EPWM3B=1 car mode compl�mentaire
    EPwm3Regs.AQCSFRC.bit.CSFB = 0;     // Action-qualifier continuous s/w force register, ignor� en mode compl�mentaire

    EPwm3Regs.PCCTL.bit.CHPEN = 0;      // PWM chopper unit disabled
    EPwm3Regs.TZDCSEL.all = 0x0000;     // All trip zone and DC compare actions disabled

    EPwm3Regs.TBCTL.bit.CTRMODE = 0x2;  // Enable the timer in count up/down mode

    //Configuration de EPWM3B en Active High Complementary Mode
    EPwm3Regs.DBCTL.bit.IN_MODE = 0;    // EPWM3A is the source for both rising-edge and falling-edge delay
    EPwm3Regs.DBCTL.bit.POLSEL = 2;     // Active High Complementary Mode (EPWM1B is inverted)
    EPwm3Regs.DBCTL.bit.OUT_MODE = 3;   // DBM is fully enabled

    //Param�trage des temps morts (ils ne sont pas centr�s)
    EPwm3Regs.DBFED.all = DT_VIENNA_PWM;           // 65ns de temps mort (half cycle d�sactiv�)
    EPwm3Regs.DBRED.all = DT_VIENNA_PWM;           // 65ns de temps mort (half cycle d�sactiv�)

//---------------------------------------------------------------------
//--- Configure ePWM4 for 250 kHz push pull waveforms pour les commandes auxiliaires
//---------------------------------------------------------------------
    EALLOW;                         // Enable EALLOW protected register access
    DevCfgRegs.SOFTPRES2.bit.EPWM4 = 1;     // ePWM4 is reset
    DevCfgRegs.SOFTPRES2.bit.EPWM4 = 0;     // ePWM4 is released from reset
    EDIS;                           // Disable EALLOW protected register access

    EPwm4Regs.TBCTL.all = 0xC003;           // Configure timer control register
// bit 15-14     11:     FREE/SOFT, 11 = ignore emulation suspend
// bit 13        0:      PHSDIR, 0 = count down after sync event
// bit 12-10     000:    CLKDIV, 000 => TBCLK = HSPCLK/1
// bit 9-7       000:    HSPCLKDIV, 000 => HSPCLK = EPWMCLK/1
// bit 6         0:      SWFSYNC, 0 = no software sync produced
// bit 5-4       00:     reserved
// bit 3         0:      PRDLD, 0 = reload PRD on counter=0
// bit 2         0:      PHSEN, 0 = phase control disabled
// bit 1-0       11:     CTRMODE, 11 = timer stopped (disabled)

    EPwm4Regs.TBCTR = 0x0000;               // Clear timer counter
    EPwm4Regs.TBPRD = PWM_VIENNA_PERIOD;        // Set timer period, shadowed by default
    EPwm4Regs.TBPHS.bit.TBPHS = 0x0000;     // Set timer phase

    EPwm4Regs.CMPCTL.all = 0x0000;          // Compare control register, shadow mode for CMPx loading
// bit 15-10     0's:    reserved
// bit 9         0:      SHDWBFULL, read-only
// bit 8         0:      SHDWAFULL, read-only
// bit 7         0:      reserved
// bit 6         0:      SHDWBMODE, don't care
// bit 5         0:      reserved
// bit 4         0:      SHDWAMODE, 0 = shadow mode
// bit 3-2       00:     LOADBMODE, don't care
// bit 1-0       10:     LOADAMODE, 00 = load on CTR=0

    //Shadow mode register pour l'Action Qualifier
    EPwm4Regs.AQCTL.bit.SHDWAQAMODE = 1;    // Action Qualifier Operates as a Double Buffer
    EPwm4Regs.AQCTL.bit.LDAQAMODE = 0;      // Load on CTR = 0
    EPwm4Regs.AQCTL.bit.LDAQASYNC = 0;      // Shadow to active load occurs according to LDAQAMODE

    EPwm4Regs.AQCTLA.all = 0x0006;      // Action-qualifier control register A
// bit 15-12     0000:   reserved
// bit 11-10     00:     CBD, 00 = do nothing
// bit 9-8       00:     CBU, 00 = do nothing
// bit 7-6       01:     CAD, 01 = clear
// bit 5-4       10:     CAU, 10 = set
// bit 3-2       00:     PRD, 00 = do nothing
// bit 1-0       00:     ZRO, 00 = do nothing

    EPwm4Regs.AQSFRC.all = 0x0000;      // Action-qualifier s/w force register
// bit 15-8      0's:    reserved
// bit 7-6       00:     RLDCSF, 00 = reload AQCSFRC on zero
// bit 5         0:      OTSFB, 0 = do not initiate a s/w forced event on output B
// bit 4-3       00:     ACTSFB, don't care
// bit 2         0:      OTSFA, 0 = do not initiate a s/w forced event on output A
// bit 1-0       00:     ACTSFA, don't care

    EPwm4Regs.AQCSFRC.all = 0x0000;     // Action-qualifier continuous s/w force register
// bit 15-4      0's:    reserved
// bit 3-2       00:     CSFB, 00 = forcing disabled
// bit 1-0       00:     CSFA, 00 = forcing disabled

    EPwm4Regs.PCCTL.bit.CHPEN = 0;      // PWM chopper unit disabled
    EPwm4Regs.TZDCSEL.all = 0x0000;     // All trip zone and DC compare actions disabled

    EPwm4Regs.TBCTL.bit.CTRMODE = 0x2;  // Enable the timer in count up/down mode

    //Configuration de EPWM4B en Active High Complementary Mode
    EPwm4Regs.DBCTL.bit.IN_MODE = 0;    // EPWM1A is the source for both rising-edge and falling-edge delay
    EPwm4Regs.DBCTL.bit.POLSEL = 2;     // Active High Complementary Mode (EPWM4B is inverted)
    EPwm4Regs.DBCTL.bit.OUT_MODE = 3;   // DBM is fully enabled

    //Param�trage des temps morts (ils ne sont pas centr�s)
    EPwm4Regs.DBFED.all = DT_CMD_AUX;           // 85% de temps mort (half cycle d�sactiv�)
    EPwm4Regs.DBRED.all = DT_CMD_AUX;           // 85% de temps mort (half cycle d�sactiv�)

//---------------------------------------------------------------------
//--- Enable the clocks to the ePWM module.                   
//--- Note: this should be done after all ePWM modules are configured
//--- to ensure synchronization between the ePWM modules.
//---------------------------------------------------------------------
	EALLOW;							// Enable EALLOW protected register access
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;	// TBCLK to ePWM modules enabled
	EDIS;							// Disable EALLOW protected register access

} // end InitEPwm()

void PwmViennaOff(void)
{
    EPwm1Regs.AQCSFRC.bit.CSFA = 1;      // Forces a continuous low on output A. In shadow mode: takes effect on the next TBCLK edge after a shadow load in the active register
    EPwm2Regs.AQCSFRC.bit.CSFA = 1;      // Forces a continuous low on output A. In shadow mode: takes effect on the next TBCLK edge after a shadow load in the active register
    EPwm3Regs.AQCSFRC.bit.CSFA = 1;      // Forces a continuous low on output A. In shadow mode: takes effect on the next TBCLK edge after a shadow load in the active register
}

void PwmViennaOn(void)
{
    EPwm1Regs.AQCSFRC.bit.CSFA = 0;      // In shadow mode: takes effect on the next TBCLK edge after a shadow load in the active register
    EPwm2Regs.AQCSFRC.bit.CSFA = 0;      // In shadow mode: takes effect on the next TBCLK edge after a shadow load in the active register
    EPwm3Regs.AQCSFRC.bit.CSFA = 0;      // In shadow mode: takes effect on the next TBCLK edge after a shadow load in the active register
 }

void PwmAuxOn(void)
{
    EPwm4Regs.AQCSFRC.bit.CSFA = 1;      // Forces a continuous low on output A. In shadow mode: takes effect on the next TBCLK edge after a shadow load in the active register
}

void PwmAuxOff(void)
{
    EPwm4Regs.AQCSFRC.bit.CSFA = 0;      //In shadow mode: takes effect on the next TBCLK edge after a shadow load in the active register
}


//--- end of file -----------------------------------------------------

/**********************************************************************
* File: SetInterrupts.c -- Solution File
* Devices: TMS320F28x8x
* Author: ACR
**********************************************************************/

#include "psu1kWvienna.h"                       // Main include file


/**********************************************************************
* Function: SetInterrupts()
*
* Description: Set interrupts using in the FW and
* enable corresponding PIE group
**********************************************************************/
void SetInterrupts()
{

       //--- Enable the Watchdog interrupt
       /*PieCtrlRegs.PIEIER1.bit.INTx8 = 1;  // Enable WAKEINT (LPM/WD) in PIE group #1
       IER |= 0x0001;                      // Enable INT1 in IER to enable PIE group 1*/

    //--- Enable the EPwm1 interrupt
        PieCtrlRegs.PIEIER3.bit.INTx1 = 1;            // Enable EPWM1 interrupt in PIE group 3
        IER |= 0x0004;                                // Enable INT3 in IER to enable PIE group
}

/********************************************************************
    Solution File for Main.c
********************************************************************/

#include "psu1kWvienna.h"                        // Main include file


/**********************************************************************
* Function: main()
*
* Description: Main function for C28x workshop labs
**********************************************************************/
void main(void)
{
//--- CPU Initialization

    /**********************************************************************
        STEP 1: Initialize System Control
        PLL, WatchDog, enable Peripheral Clocks
    ***********************************************************************/
    InitSysCtrl();                      // Initialize the CPU (FILE: SysCtrl.c)
    InitWatchdog();                     // Initialize the Watchdog Timer (FILE: WatchDog.c)

    /**********************************************************************
        STEP 2: Clear all interrupts and initialize PIE vector table
    ***********************************************************************/
    InitPieCtrl();                      // Initialize PIE control registers to their default state

    // Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

    InitPieVectTable();                 // Initialize the PIE vector table to a known state and must be executed after boot time

    /**********************************************************************
        STEP 3: Initialize GPIO, X-bars (input, output, epwm)
        Set GPIO to its default states
    ***********************************************************************/
    InitGpio();                         // Initialize the shared GPIO pins (FILE: Gpio.c)
    InitXbar();                         // Initialize the input, output & ePWM X-Bar (FILE: Xbar.c)

    /**********************************************************************
        STEP 4: Initialisation des PWM
    ***********************************************************************/
    InitEPwm();                    // Initialize PWMs (FILE: EPwm.c)

    /**********************************************************************
        STEP 5: Initialisation des ADC
    ***********************************************************************/
    InitAdca();                    // Initialize Adca (FILE: Adc.c)

    /**********************************************************************
        STEP 6: Enable the PIE module and CPU interrupts
    ***********************************************************************/
    SetInterrupts();                    // Enable individual interrupts and associated PIE group
    EnableInterrupts();                 // Enables the PIE module and CPU __interrupts � la fin de l'initialisation syst�me

//--- Main Loop
    while(1)                            // endless loop - wait for an interrupt
    {
        asm(" NOP");
        PwmViennaOn();

    }


} //end of main()


/*** end of file *****************************************************/

Regards,

Adrien

Hi Adrien and Geoffrey,

Thank you for your question!

Q: Just to be sure, does the pulse get generated at the output when not in debug mode for the assembly file?

1. If this works WITHOUT debug mode, then we should try testing with a newer version of CCS/Compiler if possible, as it may be a latent bug in the previous CCS versions.

2. If this still does not generate a pulse WITHOUT debug mode, then I would like to test with just the Compiler upgrade.

Let me know if you have any questions about these requests.

Regards,

Vince

Hi Vince,

Just to be sure, when you say "when not in debug mode", you mean to program the code in Flash and to execute it from Flash without the emulator connected ? 

I didn't try this, I'll try it and see if I have the pulse on GPIO35.

Thanks,

Adrien

Hi Vince,

I upgraded my compilateur to version v21.6.0.LTS.

I did the following tests:

1/ Execute code from flash using the linker "2838x_flash_lnk_cpu1.cmd" with PWM1 interrupt coded in C. It's working properly, I get the 1µs pulse. I measure a latency of 800ns between the trigger of the interrupt and the first instruction of the interrupt whereas I had 125ns when the code was executed from RAM.

2/ Execute code from flash using the linker "2838x_flash_lnk_cpu1.cmd" with PWM1 interrupt coded in asm. I dont' have the 1µs pulse so I don't pass through the interrupt. 

Any idea for the high latency when I execute the code from Flash ? 

Regards,

Adrien

Hi Adrien,

Thanks for the follow up and testing, that's exactly what I was looking for! The fact that the ISR doesn't run even with flash shows this is not a debugger issue. Thank you for also testing with the recent compiler, this should completely rule out any compiler issues.

This essentially leaves two potential sources for the issue (there are more, but these are the two major ones):

1. The EPWM ISR is not triggering due to an EPWM configuration issue.

    a. This is unlikely given that normal C ISR is entering/working correctly. We will come back to this if #2 below is not the case.

2. The EPWM ISR is not triggering due to an incorrect connection between the ASM file and the C main file.

    a. I believe this may be the issue. See details/next-steps below.

Next steps:

1. Can you provide your code for registering your ISR in the PIE? For example, example file has:

PieVectTable.XINT1_INT = &XINT_ASM_ISR_RAM;

2. Can you try adding an .asg call at the top of your asm file for each of your ISR functions? For example, from the top of example file:

.asg XINT_ASM_ISR_RAM, _XINT_ASM_ISR_RAM

Let me know if any questions on these, I look forward to seeing the results of this.

Regards,

Vince

Hi Vince,

I had exactly the same reflexion. Not an EPWM configuration issue as it's working in C. So I was also thinking about an incorrect connection between the ASM file and C main file and trying 1. and 2. above but no more success.

To register my ISR in the PIE, I use the generic file from C2000Ware Library "f2838x_pievect.c" and I call the function InitPieVectTable() in my main from this file ( for me, it's the same as doing PieVectTable.EPWM1_INT = &EPWM1_ISR and an easy way to initialise all the PieVectTable).

I found out this morning I pass through the asm interrupt only at the very beggining and never passes through again. I'm a little confused, I thought I had already done the test...

So I must have an issue with my assembly code, maybe I don't acknowledge the PIEACK group or clear the ePWM Interrupt Flag to enable more interrupts.

Regards,

Adrien 

Okay, I solved the problem.

There was a problem when I was clearing the bit 0 of ETCLR to enable more PWM1 interrupts.

In assembly, I was doing:

MOVZ DP, #0x4000 >> 6
OR @0xaa, #0001

But this is wrong as in Direct Addressing Mode (DP), the 6-bit offset value is concatenated with the 16-bit DP register. So it can't be more than 6 bits...

Generic statement after loading the DP register: OR @6bits_MAX, #VarA

I corrected it doing:

MOVZ DP, #4080 >> 6
OR @0x2a, #0x0001

And now it's working. We could have expected a build error on addressing mode to detect the error but that was not the case.

Thanks for your help, I brought you on the wrong way as I thought we were never passing through the interrupt.

Now let's solve the problem of latency when I execute the code from FLASH because this is not acceptable in my application.

Regards, 

Adrien

I noticed something else.

To be able to execute code from Flash, I need to put my asm isr in the section ".text". If I put my asm isr in the section ".TI.ramfunc", it's not working, I don't know why :/

I used the following generic .cmd file from the C2000Ware library:

MEMORY
{
   /* BEGIN is used for the "boot to Flash" bootloader mode   */
   BEGIN            : origin = 0x080000, length = 0x000002
   BOOT_RSVD        : origin = 0x000002, length = 0x0001AE     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x0001B0, length = 0x000250
   RAMM1            : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD0            : origin = 0x00C000, length = 0x000800
   RAMD1            : origin = 0x00C800, length = 0x000800
   RAMLS0           : origin = 0x008000, length = 0x000800
   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
   RAMLS4           : origin = 0x00A000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800
   RAMGS0           : origin = 0x00D000, length = 0x001000
   RAMGS1           : origin = 0x00E000, length = 0x001000
   RAMGS2           : origin = 0x00F000, length = 0x001000
   RAMGS3           : origin = 0x010000, length = 0x001000
   RAMGS4           : origin = 0x011000, length = 0x001000
   RAMGS5           : origin = 0x012000, length = 0x001000
   RAMGS6           : origin = 0x013000, length = 0x001000
   RAMGS7           : origin = 0x014000, length = 0x001000
   RAMGS8           : origin = 0x015000, length = 0x001000
   RAMGS9           : origin = 0x016000, length = 0x001000
   RAMGS10          : origin = 0x017000, length = 0x001000
   RAMGS11          : origin = 0x018000, length = 0x001000
   RAMGS12          : origin = 0x019000, length = 0x001000
   RAMGS13          : origin = 0x01A000, length = 0x001000
   RAMGS14          : origin = 0x01B000, length = 0x001000
   RAMGS15          : origin = 0x01C000, length = 0x001000

   /* Flash sectors */
   FLASH0           : origin = 0x080002, length = 0x001FFE  /* on-chip Flash */
   FLASH1           : origin = 0x082000, length = 0x002000  /* on-chip Flash */
   FLASH2           : origin = 0x084000, length = 0x002000  /* on-chip Flash */
   FLASH3           : origin = 0x086000, length = 0x002000  /* on-chip Flash */
   FLASH4           : origin = 0x088000, length = 0x008000  /* on-chip Flash */
   FLASH5           : origin = 0x090000, length = 0x008000  /* on-chip Flash */
   FLASH6           : origin = 0x098000, length = 0x008000  /* on-chip Flash */
   FLASH7           : origin = 0x0A0000, length = 0x008000  /* on-chip Flash */
   FLASH8           : origin = 0x0A8000, length = 0x008000  /* on-chip Flash */
   FLASH9           : origin = 0x0B0000, length = 0x008000  /* on-chip Flash */
   FLASH10          : origin = 0x0B8000, length = 0x002000  /* on-chip Flash */
   FLASH11          : origin = 0x0BA000, length = 0x002000  /* on-chip Flash */
   FLASH12          : origin = 0x0BC000, length = 0x002000  /* on-chip Flash */
   FLASH13          : origin = 0x0BE000, length = 0x002000  /* on-chip Flash */

   CPU1TOCPU2RAM   : origin = 0x03A000, length = 0x000800
   CPU2TOCPU1RAM   : origin = 0x03B000, length = 0x000800
   CPUTOCMRAM      : origin = 0x039000, length = 0x000800
   CMTOCPURAM      : origin = 0x038000, length = 0x000800

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800

   RESET            : origin = 0x3FFFC0, length = 0x000002
}

SECTIONS
{
   codestart           : > BEGIN, ALIGN(4)
   .text               : >> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(4)
   .cinit              : > FLASH4, ALIGN(4)
   .switch             : > FLASH1, ALIGN(4)
   .reset              : > RESET, TYPE = DSECT /* not used, */
   .stack              : > RAMM1

#if defined(__TI_EABI__)
   .init_array      : > FLASH1, ALIGN(4)
   .bss             : > RAMLS5
   .bss:output      : > RAMLS3
   .bss:cio         : > RAMLS5
   .data            : > RAMLS5
   .sysmem          : > RAMLS5
   /* Initalized sections go in Flash */
   .const           : > FLASH5, ALIGN(4)
#else
   .pinit           : > FLASH1, ALIGN(4)
   .ebss            : > RAMLS5
   .esysmem         : > RAMLS5
   .cio             : > RAMLS5
   /* Initalized sections go in Flash */
   .econst          : >> FLASH4 | FLASH5, ALIGN(4)
#endif

   ramgs0 : > RAMGS0, type=NOINIT
   ramgs1 : > RAMGS1, type=NOINIT
   
   MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
   MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
   MSGRAM_CPU_TO_CM    : > CPUTOCMRAM, type=NOINIT
   MSGRAM_CM_TO_CPU    : > CMTOCPURAM, type=NOINIT

   /* The following section definition are for SDFM examples */
   Filter_RegsFile  : > RAMGS0
   Filter1_RegsFile : > RAMGS1, fill=0x1111
   Filter2_RegsFile : > RAMGS2, fill=0x2222
   Filter3_RegsFile : > RAMGS3, fill=0x3333
   Filter4_RegsFile : > RAMGS4, fill=0x4444
   Difference_RegsFile : >RAMGS5, fill=0x3333

   #if defined(__TI_EABI__)
       .TI.ramfunc : {} LOAD = FLASH3,
                        RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                        LOAD_START(RamfuncsLoadStart),
                        LOAD_SIZE(RamfuncsLoadSize),
                        LOAD_END(RamfuncsLoadEnd),
                        RUN_START(RamfuncsRunStart),
                        RUN_SIZE(RamfuncsRunSize),
                        RUN_END(RamfuncsRunEnd),
                        ALIGN(4)
   #else
       .TI.ramfunc : {} LOAD = FLASH3,
                        RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                        LOAD_START(_RamfuncsLoadStart),
                        LOAD_SIZE(_RamfuncsLoadSize),
                        LOAD_END(_RamfuncsLoadEnd),
                        RUN_START(_RamfuncsRunStart),
                        RUN_SIZE(_RamfuncsRunSize),
                        RUN_END(_RamfuncsRunEnd),
                        ALIGN(4)
   #endif

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Any idea why it's not working ?

Thanks,

Adrien

Hi Adrien,

Glad that the reason for the ISR entry problem was found.

I will split up the two issues and first address the latency issue. For the .cmd file, I will contact the .cmd file expert to help with this as that is not my strong suit, after I've addressed the latency. I will also ping a Flash expert to double-check my understanding on the latency.

Latency Issue:

The 800ns delay is likely not related to the "save context" operations of the ISR. This is given the number of registers needed to be saved is low, and not nearly enough to contribute to ~600ns of extra delay.

My guess is that the delay is due to the flash code-fetch time being higher because the ISR code is in a different location (as you mentioned). If we can resolve this, we can likely get the timing back to expected levels (default example using Flash only needs a 135ns delay).

Let me contact the .cmd file owner first, and if that doesn't resolve it, we can sync with Flash owner on wait-state delays.

Regards,

Vince

Hi Adrien,

Regarding the cmd issue, can you share the .map file?

When you say "it's not working", are you getting any build errors? Or the  ISR code is unavailable in the specified RAM location?

Regards,

Veena

Hi Vince, hi Veena,

@Vince, I don't get the extra delay anymore (maybe something went wrong when I did the measurement).

@Veena, you'll find the answer to your questions in part 4 below

Here is a clear overview of all configurations I tried (compiler version: v21.6.0.LST, clock: 190MHz):

1/ Program running from RAM with emulator connected / Linker: "2838x_RAM_combined_lnk_cpu1.cmd" from C2000Ware library

ISR coded in C. Latency between trigger of PWM1 and rising edge (begin of jitter) of 1µs pulse : ~123ns, jitter in the rising edge ~25ns (~5 clock pulses)

2/ Program running from RAM with emulator connected / Linker: "2838x_RAM_combined_lnk_cpu1.cmd" from C2000Ware library

ISR coded in asm (no register saved at the beginning of the interrupt). Latency between trigger of PWM1 and rising edge (begin of jitter) of 1µs pulse : ~96ns, jitter in the rising edge ~25ns (~5 clock pulses)

3/ Program running from FLASH / Linker: "2838x_flash_lnk_cpu1.cmd" from C2000Ware library

ISR coded in C. Latency between trigger of PWM1 and rising edge (begin of jitter) of 1µs pulse : ~223ns (extra 100ns), jitter in the rising edge ~30ns (~6 clock pulses)

4/ Program running from FLASH / Linker: "2838x_flash_lnk_cpu1.cmd" from C2000Ware library

ISR coded in asm. ISR in .sect ".TI.ramfunc". Below, extract of .cmd file regarding the section ".TI.ramfunc":

.TI.ramfunc : {} LOAD = FLASH3,
                 RUN = RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3,
                 LOAD_START(_RamfuncsLoadStart),
                 LOAD_SIZE(_RamfuncsLoadSize),
                 LOAD_END(_RamfuncsLoadEnd),
                 RUN_START(_RamfuncsRunStart),
                 RUN_SIZE(_RamfuncsRunSize),
                 RUN_END(_RamfuncsRunEnd),
                 ALIGN(4)

No build error. ISR is not running, I don't have the 1µs pulse.

Here is the .map file:

******************************************************************************
             TMS320C2000 Linker PC v21.6.0                     
******************************************************************************
>> Linked Wed Feb 23 10:16:58 2022

OUTPUT FILE NAME:   <psu1kWvienna_F2838x.out>
ENTRY POINT SYMBOL: "_c_int00"  address: 00082f1e


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  BOOT_RSVD             00000002   000001ae  00000000  000001ae  RWIX
  RAMM0                 000001b0   00000250  00000000  00000250  RWIX
  RAMM1                 00000400   00000400  00000200  00000200  RWIX
  ADCA_RESULT           00000b00   00000020  00000018  00000008  RWIX
  ADCB_RESULT           00000b20   00000020  00000018  00000008  RWIX
  ADCC_RESULT           00000b40   00000020  00000018  00000008  RWIX
  ADCD_RESULT           00000b60   00000020  00000018  00000008  RWIX
  CPU_TIMER0            00000c00   00000008  00000008  00000000  RWIX
  CPU_TIMER1            00000c08   00000008  00000008  00000000  RWIX
  CPU_TIMER2            00000c10   00000008  00000008  00000000  RWIX
  PIE_CTRL              00000ce0   00000020  0000001a  00000006  RWIX
  PIE_VECT_TABLE        00000d00   00000200  000001c0  00000040  RWIX
  DMA                   00001000   000000e0  000000e0  00000000  RWIX
  CLA1                  00001400   00000048  00000048  00000000  RWIX
  EPWM1                 00004000   00000100  00000100  00000000  RWIX
  EPWM2                 00004100   00000100  00000100  00000000  RWIX
  EPWM3                 00004200   00000100  00000100  00000000  RWIX
  EPWM4                 00004300   00000100  00000100  00000000  RWIX
  EPWM5                 00004400   00000100  00000100  00000000  RWIX
  EPWM6                 00004500   00000100  00000100  00000000  RWIX
  EPWM7                 00004600   00000100  00000100  00000000  RWIX
  EPWM8                 00004700   00000100  00000100  00000000  RWIX
  EPWM9                 00004800   00000100  00000100  00000000  RWIX
  EPWM10                00004900   00000100  00000100  00000000  RWIX
  EPWM11                00004a00   00000100  00000100  00000000  RWIX
  EPWM12                00004b00   00000100  00000100  00000000  RWIX
  EPWM13                00004c00   00000100  00000100  00000000  RWIX
  EPWM14                00004d00   00000100  00000100  00000000  RWIX
  EPWM15                00004e00   00000100  00000100  00000000  RWIX
  EPWM16                00004f00   00000100  00000100  00000000  RWIX
  EQEP1                 00005100   00000040  00000038  00000008  RWIX
  EQEP2                 00005140   00000040  00000038  00000008  RWIX
  EQEP3                 00005180   00000040  00000038  00000008  RWIX
  ECAP1                 00005200   00000020  00000020  00000000  RWIX
  ECAP2                 00005240   00000020  00000020  00000000  RWIX
  ECAP3                 00005280   00000020  00000020  00000000  RWIX
  ECAP4                 000052c0   00000020  00000020  00000000  RWIX
  ECAP5                 00005300   00000020  00000020  00000000  RWIX
  ECAP6                 00005340   00000020  00000020  00000000  RWIX
  HRCAP6                00005360   00000020  00000016  0000000a  RWIX
  ECAP7                 00005380   00000020  00000020  00000000  RWIX
  HRCAP7                000053a0   00000020  00000016  0000000a  RWIX
  DACA                  00005c00   00000010  00000007  00000009  RWIX
  DACB                  00005c10   00000010  00000007  00000009  RWIX
  DACC                  00005c20   00000010  00000007  00000009  RWIX
  CMPSS1                00005c80   00000020  0000001b  00000005  RWIX
  CMPSS2                00005ca0   00000020  0000001b  00000005  RWIX
  CMPSS3                00005cc0   00000020  0000001b  00000005  RWIX
  CMPSS4                00005ce0   00000020  0000001b  00000005  RWIX
  CMPSS5                00005d00   00000020  0000001b  00000005  RWIX
  CMPSS6                00005d20   00000020  0000001b  00000005  RWIX
  CMPSS7                00005d40   00000020  0000001b  00000005  RWIX
  CMPSS8                00005d60   00000020  0000001b  00000005  RWIX
  SDFM1                 00005e00   00000080  00000080  00000000  RWIX
  SDFM2                 00005e80   00000080  00000080  00000000  RWIX
  MCBSPA                00006000   00000040  00000024  0000001c  RWIX
  MCBSPB                00006040   00000040  00000024  0000001c  RWIX
  SPIA                  00006100   00000010  00000010  00000000  RWIX
  SPIB                  00006110   00000010  00000010  00000000  RWIX
  SPIC                  00006120   00000010  00000010  00000000  RWIX
  SPID                  00006130   00000010  00000010  00000000  RWIX
  BGCRC                 00006340   00000080  00000080  00000000  RWIX
  PMBUSA                00006400   00000020  0000001e  00000002  RWIX
  FSITXA                00006600   00000080  00000042  0000003e  RWIX
  FSIRXA                00006680   00000080  00000042  0000003e  RWIX
  FSI_TXB               00006700   00000080  00000042  0000003e  RWIX
  FSI_RXB               00006780   00000080  00000042  0000003e  RWIX
  FSI_RXC               00006880   00000080  00000042  0000003e  RWIX
  FSI_RXD               00006980   00000080  00000042  0000003e  RWIX
  FSI_RXE               00006a80   00000080  00000042  0000003e  RWIX
  FSI_RXF               00006b80   00000080  00000042  0000003e  RWIX
  FSI_RXG               00006c80   00000080  00000042  0000003e  RWIX
  FSI_RXH               00006d80   00000080  00000042  0000003e  RWIX
  WD                    00007000   00000040  0000002b  00000015  RWIX
  NMIINTRUPT            00007060   00000010  0000000c  00000004  RWIX
  XINT                  00007070   00000010  0000000b  00000005  RWIX
  SCIA                  00007200   00000010  00000010  00000000  RWIX
  SCIB                  00007210   00000010  00000010  00000000  RWIX
  SCIC                  00007220   00000010  00000010  00000000  RWIX
  SCID                  00007230   00000010  00000010  00000000  RWIX
  I2CA                  00007300   00000040  00000022  0000001e  RWIX
  I2CB                  00007340   00000040  00000022  0000001e  RWIX
  ADCA                  00007400   00000080  0000007c  00000004  RWIX
  ADCB                  00007480   00000080  0000007c  00000004  RWIX
  ADCC                  00007500   00000080  0000007c  00000004  RWIX
  ADCD                  00007580   00000080  0000007c  00000004  RWIX
  INPUT_XBAR            00007900   00000020  00000020  00000000  RWIX
  XBAR                  00007920   00000020  00000010  00000010  RWIX
  SYNC_SOC              00007940   00000010  00000006  0000000a  RWIX
  DMA_CLA_SRC_SEL       00007980   00000040  0000001a  00000026  RWIX
  EPWM_XBAR             00007a00   00000040  00000040  00000000  RWIX
  OUTPUT_XBAR           00007a80   00000040  00000040  00000000  RWIX
  GPIOCTRL              00007c00   00000180  00000180  00000000  RWIX
  GPIODATA              00007f00   00000030  00000030  00000000  RWIX
  RAMLS0                00008000   00000800  00000010  000007f0  RWIX
  RAMLS1                00008800   00000800  00000000  00000800  RWIX
  RAMLS2                00009000   00000800  00000000  00000800  RWIX
  RAMLS3                00009800   00000800  00000000  00000800  RWIX
  RAMLS4                0000a000   00000800  00000000  00000800  RWIX
  RAMLS5                0000a800   00000800  0000000a  000007f6  RWIX
  RAMLS6                0000b000   00000800  00000000  00000800  RWIX
  RAMLS7                0000b800   00000800  00000000  00000800  RWIX
  RAMD0                 0000c000   00000800  00000000  00000800  RWIX
  RAMD1                 0000c800   00000800  00000000  00000800  RWIX
  RAMGS0                0000d000   00001000  00000000  00001000  RWIX
  RAMGS1                0000e000   00001000  00000000  00001000  RWIX
  RAMGS2                0000f000   00001000  00000000  00001000  RWIX
  RAMGS3                00010000   00001000  00000000  00001000  RWIX
  RAMGS4                00011000   00001000  00000000  00001000  RWIX
  RAMGS5                00012000   00001000  00000000  00001000  RWIX
  RAMGS6                00013000   00001000  00000000  00001000  RWIX
  RAMGS7                00014000   00001000  00000000  00001000  RWIX
  RAMGS8                00015000   00001000  00000000  00001000  RWIX
  RAMGS9                00016000   00001000  00000000  00001000  RWIX
  RAMGS10               00017000   00001000  00000000  00001000  RWIX
  RAMGS11               00018000   00001000  00000000  00001000  RWIX
  RAMGS12               00019000   00001000  00000000  00001000  RWIX
  RAMGS13               0001a000   00001000  00000000  00001000  RWIX
  RAMGS14               0001b000   00001000  00000000  00001000  RWIX
  RAMGS15               0001c000   00001000  00000000  00001000  RWIX
  CMTOCPURAM            00038000   00000800  00000000  00000800  RWIX
  CPUTOCMRAM            00039000   00000800  00000000  00000800  RWIX
  CPU1TOCPU2RAM         0003a000   00000800  00000000  00000800  RWIX
  CPU2TOCPU1RAM         0003b000   00000800  00000000  00000800  RWIX
  EMIF1                 00047000   00000800  00000028  000007d8  RWIX
  EMIF2                 00047800   00000800  00000028  000007d8  RWIX
  CANA                  00048000   00000800  00000162  0000069e  RWIX
  CANA_MSG_RAM          00049000   00000800  00000000  00000800  RWIX
  CANB                  0004a000   00000800  00000162  0000069e  RWIX
  CANB_MSG_RAM          0004b000   00000800  00000000  00000800  RWIX
  ECATSS                00057e00   00000100  00000024  000000dc  RWIX
  ECATSS_CONFIG         00057f00   00000100  00000016  000000ea  RWIX
  MCANSS                0005c400   00000040  00000016  0000002a  RWIX
  MCAN                  0005c600   00000200  0000007e  00000182  RWIX
  MCAN_ERROR            0005c800   00000400  00000108  000002f8  RWIX
  CPU1TOCPU2_IPC_CPU1VI 0005ce00   00000040  00000026  0000001a  RWIX
  CPU1TOCM_IPC_CPU1VIEW 0005ce40   00000040  00000024  0000001c  RWIX
  DEV_CFG               0005d000   000001a0  000001a0  00000000  RWIX
  CLK_CFG               0005d200   00000100  0000003a  000000c6  RWIX
  CPU_SYS               0005d300   00000100  000000a0  00000060  RWIX
  SYS_STATUS            0005d400   00000100  00000018  000000e8  RWIX
  PERIPH_AC             0005d500   00000200  00000200  00000000  RWIX
  ANALOG_SUBSYS         0005d700   00000100  000000e2  0000001e  RWIX
  CM_CONF               0005dc00   00000400  00000400  00000000  RWIX
  HWBIST                0005e000   000000d0  0000008e  00000042  RWIX
  DCC0                  0005e700   00000040  0000002c  00000014  RWIX
  DCC1                  0005e740   00000040  0000002c  00000014  RWIX
  DCC2                  0005e780   00000040  0000002c  00000014  RWIX
  ERAD_GLOBAL_REGISTERS 0005e800   00000100  00000014  000000ec  RWIX
  ERAD_HWBP_REGISTERS   0005e900   00000080  00000008  00000078  RWIX
  ERAD_COUNTER_REGISTER 0005e980   00000080  0000000c  00000074  RWIX
  ERAD_CRC_REGISTERS    0005ea00   00000100  00000006  000000fa  RWIX
  DCSM_Z1               0005f000   00000040  0000003e  00000002  RWIX
  DCSM_Z2               0005f080   00000040  0000002c  00000014  RWIX
  DCSM_COMMON           0005f0c0   00000040  0000001e  00000022  RWIX
  MEMCFG                0005f400   000000c0  000000ae  00000012  RWIX
  EMIF1CONFIG           0005f4c0   00000020  0000000a  00000016  RWIX
  EMIF2CONFIG           0005f4e0   00000020  0000000a  00000016  RWIX
  ACCESSPROTECTION      0005f500   00000040  0000002e  00000012  RWIX
  MEMORYERROR           0005f540   00000040  0000003a  00000006  RWIX
  ROMWAITSTATE          0005f580   00000008  00000002  00000006  RWIX
  ROMPREFETCH           0005f588   00000008  00000002  00000006  RWIX
  TEST_ERROR            0005f590   0000000f  00000006  00000009  RWIX
  FLASH0_CTRL           0005f800   00000300  00000182  0000017e  RWIX
  FLASH0_ECC            0005fb00   00000040  00000028  00000018  RWIX
  DCSM_Z1_OTP           00078000   00000020  00000020  00000000  RWIX
  DCSM_Z2_OTP           00078200   00000020  00000014  0000000c  RWIX
  BEGIN                 00080000   00000002  00000002  00000000  RWIX
  FLASH0                00080002   00001ffe  00000000  00001ffe  RWIX
  FLASH1                00082000   00002000  000019a1  0000065f  RWIX
  FLASH2                00084000   00002000  00000000  00002000  RWIX
  FLASH3                00086000   00002000  00000010  00001ff0  RWIX
  FLASH4                00088000   00008000  000001da  00007e26  RWIX
  FLASH5                00090000   00008000  00000000  00008000  RWIX
  FLASH6                00098000   00008000  00000000  00008000  RWIX
  FLASH7                000a0000   00008000  00000000  00008000  RWIX
  FLASH8                000a8000   00008000  00000000  00008000  RWIX
  FLASH9                000b0000   00008000  00000000  00008000  RWIX
  FLASH10               000b8000   00002000  00000000  00002000  RWIX
  FLASH11               000ba000   00002000  00000000  00002000  RWIX
  FLASH12               000bc000   00002000  00000000  00002000  RWIX
  FLASH13               000be000   00002000  00000000  00002000  RWIX
  RESET                 003fffc0   00000002  00000000  00000002  RWIX


SECTION ALLOCATION MAP

 output                                  attributes/
section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------
codestart 
*          0    00080000    00000002     
                  00080000    00000002     F2838x_CodeStartBranch.obj (codestart)

.cinit     0    00088000    0000001a     
                  00088000    0000000e     rts2800_fpu32.lib : exit.c.obj (.cinit)
                  0008800e    00000005                       : _lock.c.obj (.cinit:__lock)
                  00088013    00000005                       : _lock.c.obj (.cinit:__unlock)
                  00088018    00000002     --HOLE-- [fill = 0]

.reset     0    003fffc0    00000002     DSECT
                  003fffc0    00000002     rts2800_fpu32.lib : boot28.asm.obj (.reset)

.stack     0    00000400    00000200     UNINITIALIZED
                  00000400    00000200     --HOLE--

.pinit     0    00082000    00000000     UNINITIALIZED

.ebss      0    0000a800    0000000a     UNINITIALIZED
                  0000a800    00000006     rts2800_fpu32.lib : exit.c.obj (.ebss)
                  0000a806    00000002                       : _lock.c.obj (.ebss:__lock)
                  0000a808    00000002                       : _lock.c.obj (.ebss:__unlock)

AdcaResultFile 
*          0    00000b00    00000018     UNINITIALIZED
                  00000b00    00000018     f2838x_GlobalVariableDefs.obj (AdcaResultFile)

AdcbResultFile 
*          0    00000b20    00000018     UNINITIALIZED
                  00000b20    00000018     f2838x_GlobalVariableDefs.obj (AdcbResultFile)

AdccResultFile 
*          0    00000b40    00000018     UNINITIALIZED
                  00000b40    00000018     f2838x_GlobalVariableDefs.obj (AdccResultFile)

AdcdResultFile 
*          0    00000b60    00000018     UNINITIALIZED
                  00000b60    00000018     f2838x_GlobalVariableDefs.obj (AdcdResultFile)

CpuTimer0RegsFile 
*          0    00000c00    00000008     UNINITIALIZED
                  00000c00    00000008     f2838x_GlobalVariableDefs.obj (CpuTimer0RegsFile)

CpuTimer1RegsFile 
*          0    00000c08    00000008     UNINITIALIZED
                  00000c08    00000008     f2838x_GlobalVariableDefs.obj (CpuTimer1RegsFile)

CpuTimer2RegsFile 
*          0    00000c10    00000008     UNINITIALIZED
                  00000c10    00000008     f2838x_GlobalVariableDefs.obj (CpuTimer2RegsFile)

PieCtrlRegsFile 
*          0    00000ce0    0000001a     UNINITIALIZED
                  00000ce0    0000001a     f2838x_GlobalVariableDefs.obj (PieCtrlRegsFile)

PieVectTableFile 
*          0    00000d00    000001c0     UNINITIALIZED
                  00000d00    000001c0     f2838x_GlobalVariableDefs.obj (PieVectTableFile)

EmuKeyVar 
*          0    00000d00    00000000     UNINITIALIZED

EmuBModeVar 
*          0    00000d00    00000001     UNINITIALIZED
                  00000d00    00000001     f2838x_GlobalVariableDefs.obj (EmuBModeVar)

EmuBootPinsVar 
*          0    00000d01    00000001     UNINITIALIZED
                  00000d01    00000001     f2838x_GlobalVariableDefs.obj (EmuBootPinsVar)

FlashCallbackVar 
*          0    00000d02    00000000     UNINITIALIZED

FlashScalingVar 
*          0    00000d02    00000000     UNINITIALIZED

DmaRegsFile 
*          0    00001000    000000e0     UNINITIALIZED
                  00001000    000000e0     f2838x_GlobalVariableDefs.obj (DmaRegsFile)

Cla1RegsFile 
*          0    00001400    00000048     UNINITIALIZED
                  00001400    00000048     f2838x_GlobalVariableDefs.obj (Cla1RegsFile)

EPwm1RegsFile 
*          0    00004000    00000100     UNINITIALIZED
                  00004000    00000100     f2838x_GlobalVariableDefs.obj (EPwm1RegsFile)

EPwm2RegsFile 
*          0    00004100    00000100     UNINITIALIZED
                  00004100    00000100     f2838x_GlobalVariableDefs.obj (EPwm2RegsFile)

EPwm3RegsFile 
*          0    00004200    00000100     UNINITIALIZED
                  00004200    00000100     f2838x_GlobalVariableDefs.obj (EPwm3RegsFile)

EPwm4RegsFile 
*          0    00004300    00000100     UNINITIALIZED
                  00004300    00000100     f2838x_GlobalVariableDefs.obj (EPwm4RegsFile)

EPwm5RegsFile 
*          0    00004400    00000100     UNINITIALIZED
                  00004400    00000100     f2838x_GlobalVariableDefs.obj (EPwm5RegsFile)

EPwm6RegsFile 
*          0    00004500    00000100     UNINITIALIZED
                  00004500    00000100     f2838x_GlobalVariableDefs.obj (EPwm6RegsFile)

EPwm7RegsFile 
*          0    00004600    00000100     UNINITIALIZED
                  00004600    00000100     f2838x_GlobalVariableDefs.obj (EPwm7RegsFile)

EPwm8RegsFile 
*          0    00004700    00000100     UNINITIALIZED
                  00004700    00000100     f2838x_GlobalVariableDefs.obj (EPwm8RegsFile)

EPwm9RegsFile 
*          0    00004800    00000100     UNINITIALIZED
                  00004800    00000100     f2838x_GlobalVariableDefs.obj (EPwm9RegsFile)

EPwm10RegsFile 
*          0    00004900    00000100     UNINITIALIZED
                  00004900    00000100     f2838x_GlobalVariableDefs.obj (EPwm10RegsFile)

EPwm11RegsFile 
*          0    00004a00    00000100     UNINITIALIZED
                  00004a00    00000100     f2838x_GlobalVariableDefs.obj (EPwm11RegsFile)

EPwm12RegsFile 
*          0    00004b00    00000100     UNINITIALIZED
                  00004b00    00000100     f2838x_GlobalVariableDefs.obj (EPwm12RegsFile)

EPwm13RegsFile 
*          0    00004c00    00000100     UNINITIALIZED
                  00004c00    00000100     f2838x_GlobalVariableDefs.obj (EPwm13RegsFile)

EPwm14RegsFile 
*          0    00004d00    00000100     UNINITIALIZED
                  00004d00    00000100     f2838x_GlobalVariableDefs.obj (EPwm14RegsFile)

EPwm15RegsFile 
*          0    00004e00    00000100     UNINITIALIZED
                  00004e00    00000100     f2838x_GlobalVariableDefs.obj (EPwm15RegsFile)

EPwm16RegsFile 
*          0    00004f00    00000100     UNINITIALIZED
                  00004f00    00000100     f2838x_GlobalVariableDefs.obj (EPwm16RegsFile)

EQep1RegsFile 
*          0    00005100    00000038     UNINITIALIZED
                  00005100    00000038     f2838x_GlobalVariableDefs.obj (EQep1RegsFile)

EQep2RegsFile 
*          0    00005140    00000038     UNINITIALIZED
                  00005140    00000038     f2838x_GlobalVariableDefs.obj (EQep2RegsFile)

EQep3RegsFile 
*          0    00005180    00000038     UNINITIALIZED
                  00005180    00000038     f2838x_GlobalVariableDefs.obj (EQep3RegsFile)

ECap1RegsFile 
*          0    00005200    00000020     UNINITIALIZED
                  00005200    00000020     f2838x_GlobalVariableDefs.obj (ECap1RegsFile)

ECap2RegsFile 
*          0    00005240    00000020     UNINITIALIZED
                  00005240    00000020     f2838x_GlobalVariableDefs.obj (ECap2RegsFile)

ECap3RegsFile 
*          0    00005280    00000020     UNINITIALIZED
                  00005280    00000020     f2838x_GlobalVariableDefs.obj (ECap3RegsFile)

ECap4RegsFile 
*          0    000052c0    00000020     UNINITIALIZED
                  000052c0    00000020     f2838x_GlobalVariableDefs.obj (ECap4RegsFile)

ECap5RegsFile 
*          0    00005300    00000020     UNINITIALIZED
                  00005300    00000020     f2838x_GlobalVariableDefs.obj (ECap5RegsFile)

ECap6RegsFile 
*          0    00005340    00000020     UNINITIALIZED
                  00005340    00000020     f2838x_GlobalVariableDefs.obj (ECap6RegsFile)

HRCap6RegsFile 
*          0    00005360    00000016     UNINITIALIZED
                  00005360    00000016     f2838x_GlobalVariableDefs.obj (HRCap6RegsFile)

ECap7RegsFile 
*          0    00005380    00000020     UNINITIALIZED
                  00005380    00000020     f2838x_GlobalVariableDefs.obj (ECap7RegsFile)

HRCap7RegsFile 
*          0    000053a0    00000016     UNINITIALIZED
                  000053a0    00000016     f2838x_GlobalVariableDefs.obj (HRCap7RegsFile)

DacaRegsFile 
*          0    00005c00    00000007     UNINITIALIZED
                  00005c00    00000007     f2838x_GlobalVariableDefs.obj (DacaRegsFile)

DacbRegsFile 
*          0    00005c10    00000007     UNINITIALIZED
                  00005c10    00000007     f2838x_GlobalVariableDefs.obj (DacbRegsFile)

DaccRegsFile 
*          0    00005c20    00000007     UNINITIALIZED
                  00005c20    00000007     f2838x_GlobalVariableDefs.obj (DaccRegsFile)

Cmpss1RegsFile 
*          0    00005c80    0000001b     UNINITIALIZED
                  00005c80    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss1RegsFile)

Cmpss2RegsFile 
*          0    00005ca0    0000001b     UNINITIALIZED
                  00005ca0    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss2RegsFile)

Cmpss3RegsFile 
*          0    00005cc0    0000001b     UNINITIALIZED
                  00005cc0    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss3RegsFile)

Cmpss4RegsFile 
*          0    00005ce0    0000001b     UNINITIALIZED
                  00005ce0    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss4RegsFile)

Cmpss5RegsFile 
*          0    00005d00    0000001b     UNINITIALIZED
                  00005d00    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss5RegsFile)

Cmpss6RegsFile 
*          0    00005d20    0000001b     UNINITIALIZED
                  00005d20    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss6RegsFile)

Cmpss7RegsFile 
*          0    00005d40    0000001b     UNINITIALIZED
                  00005d40    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss7RegsFile)

Cmpss8RegsFile 
*          0    00005d60    0000001b     UNINITIALIZED
                  00005d60    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss8RegsFile)

Sdfm1RegsFile 
*          0    00005e00    00000080     UNINITIALIZED
                  00005e00    00000080     f2838x_GlobalVariableDefs.obj (Sdfm1RegsFile)

Sdfm2RegsFile 
*          0    00005e80    00000080     UNINITIALIZED
                  00005e80    00000080     f2838x_GlobalVariableDefs.obj (Sdfm2RegsFile)

McbspaRegsFile 
*          0    00006000    00000024     UNINITIALIZED
                  00006000    00000024     f2838x_GlobalVariableDefs.obj (McbspaRegsFile)

McbspbRegsFile 
*          0    00006040    00000024     UNINITIALIZED
                  00006040    00000024     f2838x_GlobalVariableDefs.obj (McbspbRegsFile)

SpiaRegsFile 
*          0    00006100    00000010     UNINITIALIZED
                  00006100    00000010     f2838x_GlobalVariableDefs.obj (SpiaRegsFile)

SpibRegsFile 
*          0    00006110    00000010     UNINITIALIZED
                  00006110    00000010     f2838x_GlobalVariableDefs.obj (SpibRegsFile)

SpicRegsFile 
*          0    00006120    00000010     UNINITIALIZED
                  00006120    00000010     f2838x_GlobalVariableDefs.obj (SpicRegsFile)

SpidRegsFile 
*          0    00006130    00000010     UNINITIALIZED
                  00006130    00000010     f2838x_GlobalVariableDefs.obj (SpidRegsFile)

BgcrcRegsFile 
*          0    00006340    00000080     UNINITIALIZED
                  00006340    00000080     f2838x_GlobalVariableDefs.obj (BgcrcRegsFile)

FsiTxaRegsFile 
*          0    00006600    00000042     UNINITIALIZED
                  00006600    00000042     f2838x_GlobalVariableDefs.obj (FsiTxaRegsFile)

FsiRxaRegsFile 
*          0    00006680    00000042     UNINITIALIZED
                  00006680    00000042     f2838x_GlobalVariableDefs.obj (FsiRxaRegsFile)

FsiTxbRegsFile 
*          0    00006700    00000042     UNINITIALIZED
                  00006700    00000042     f2838x_GlobalVariableDefs.obj (FsiTxbRegsFile)

FsiRxbRegsFile 
*          0    00006780    00000042     UNINITIALIZED
                  00006780    00000042     f2838x_GlobalVariableDefs.obj (FsiRxbRegsFile)

FsiRxcRegsFile 
*          0    00006880    00000042     UNINITIALIZED
                  00006880    00000042     f2838x_GlobalVariableDefs.obj (FsiRxcRegsFile)

FsiRxdRegsFile 
*          0    00006980    00000042     UNINITIALIZED
                  00006980    00000042     f2838x_GlobalVariableDefs.obj (FsiRxdRegsFile)

FsiRxeRegsFile 
*          0    00006a80    00000042     UNINITIALIZED
                  00006a80    00000042     f2838x_GlobalVariableDefs.obj (FsiRxeRegsFile)

FsiRxfRegsFile 
*          0    00006b80    00000042     UNINITIALIZED
                  00006b80    00000042     f2838x_GlobalVariableDefs.obj (FsiRxfRegsFile)

FsiRxgRegsFile 
*          0    00006c80    00000042     UNINITIALIZED
                  00006c80    00000042     f2838x_GlobalVariableDefs.obj (FsiRxgRegsFile)

FsiRxhRegsFile 
*          0    00006d80    00000042     UNINITIALIZED
                  00006d80    00000042     f2838x_GlobalVariableDefs.obj (FsiRxhRegsFile)

WdRegsFile 
*          0    00007000    0000002b     UNINITIALIZED
                  00007000    0000002b     f2838x_GlobalVariableDefs.obj (WdRegsFile)

NmiIntruptRegsFile 
*          0    00007060    0000000c     UNINITIALIZED
                  00007060    0000000c     f2838x_GlobalVariableDefs.obj (NmiIntruptRegsFile)

XintRegsFile 
*          0    00007070    0000000b     UNINITIALIZED
                  00007070    0000000b     f2838x_GlobalVariableDefs.obj (XintRegsFile)

I2caRegsFile 
*          0    00007300    00000022     UNINITIALIZED
                  00007300    00000022     f2838x_GlobalVariableDefs.obj (I2caRegsFile)

I2cbRegsFile 
*          0    00007340    00000022     UNINITIALIZED
                  00007340    00000022     f2838x_GlobalVariableDefs.obj (I2cbRegsFile)

AdcaRegsFile 
*          0    00007400    0000007c     UNINITIALIZED
                  00007400    0000007c     f2838x_GlobalVariableDefs.obj (AdcaRegsFile)

AdcbRegsFile 
*          0    00007480    0000007c     UNINITIALIZED
                  00007480    0000007c     f2838x_GlobalVariableDefs.obj (AdcbRegsFile)

AdccRegsFile 
*          0    00007500    0000007c     UNINITIALIZED
                  00007500    0000007c     f2838x_GlobalVariableDefs.obj (AdccRegsFile)

AdcdRegsFile 
*          0    00007580    0000007c     UNINITIALIZED
                  00007580    0000007c     f2838x_GlobalVariableDefs.obj (AdcdRegsFile)

InputXbarRegsFile 
*          0    00007900    00000020     UNINITIALIZED
                  00007900    00000020     f2838x_GlobalVariableDefs.obj (InputXbarRegsFile)

XbarRegsFile 
*          0    00007920    00000010     UNINITIALIZED
                  00007920    00000010     f2838x_GlobalVariableDefs.obj (XbarRegsFile)

SyncSocRegsFile 
*          0    00007940    00000006     UNINITIALIZED
                  00007940    00000006     f2838x_GlobalVariableDefs.obj (SyncSocRegsFile)

EPwmXbarRegsFile 
*          0    00007a00    00000040     UNINITIALIZED
                  00007a00    00000040     f2838x_GlobalVariableDefs.obj (EPwmXbarRegsFile)

OutputXbarRegsFile 
*          0    00007a80    00000040     UNINITIALIZED
                  00007a80    00000040     f2838x_GlobalVariableDefs.obj (OutputXbarRegsFile)

GpioCtrlRegsFile 
*          0    00007c00    00000180     UNINITIALIZED
                  00007c00    00000180     f2838x_GlobalVariableDefs.obj (GpioCtrlRegsFile)

GpioDataRegsFile 
*          0    00007f00    00000030     UNINITIALIZED
                  00007f00    00000030     f2838x_GlobalVariableDefs.obj (GpioDataRegsFile)

Emif1RegsFile 
*          0    00047000    00000028     UNINITIALIZED
                  00047000    00000028     f2838x_GlobalVariableDefs.obj (Emif1RegsFile)

Emif2RegsFile 
*          0    00047800    00000028     UNINITIALIZED
                  00047800    00000028     f2838x_GlobalVariableDefs.obj (Emif2RegsFile)

CanaRegsFile 
*          0    00048000    00000162     UNINITIALIZED
                  00048000    00000162     f2838x_GlobalVariableDefs.obj (CanaRegsFile)

CanbRegsFile 
*          0    0004a000    00000162     UNINITIALIZED
                  0004a000    00000162     f2838x_GlobalVariableDefs.obj (CanbRegsFile)

EcatssRegsFile 
*          0    00057e00    00000024     UNINITIALIZED
                  00057e00    00000024     f2838x_GlobalVariableDefs.obj (EcatssRegsFile)

EcatssConfigRegsFile 
*          0    00057f00    00000016     UNINITIALIZED
                  00057f00    00000016     f2838x_GlobalVariableDefs.obj (EcatssConfigRegsFile)

McanssRegsFile 
*          0    0005c400    00000016     UNINITIALIZED
                  0005c400    00000016     f2838x_GlobalVariableDefs.obj (McanssRegsFile)

McanRegsFile 
*          0    0005c600    0000007e     UNINITIALIZED
                  0005c600    0000007e     f2838x_GlobalVariableDefs.obj (McanRegsFile)

McanErrorRegsFile 
*          0    0005c800    00000108     UNINITIALIZED
                  0005c800    00000108     f2838x_GlobalVariableDefs.obj (McanErrorRegsFile)

IpcRegsCPUFile 
*          0    0005ce00    00000026     UNINITIALIZED
                  0005ce00    00000026     f2838x_GlobalVariableDefs.obj (IpcRegsCPUFile)

IpcRegsCMFile 
*          0    0005ce40    00000024     UNINITIALIZED
                  0005ce40    00000024     f2838x_GlobalVariableDefs.obj (IpcRegsCMFile)

SysStatusRegsFile 
*          0    0005d400    00000018     UNINITIALIZED
                  0005d400    00000018     f2838x_GlobalVariableDefs.obj (SysStatusRegsFile)

AnalogSubsysRegsFile 
*          0    0005d700    000000e2     UNINITIALIZED
                  0005d700    000000e2     f2838x_GlobalVariableDefs.obj (AnalogSubsysRegsFile)

HwbistRegsFile 
*          0    0005e000    0000008e     UNINITIALIZED
                  0005e000    0000008e     f2838x_GlobalVariableDefs.obj (HwbistRegsFile)

Dcc0RegsFile 
*          0    0005e700    0000002c     UNINITIALIZED
                  0005e700    0000002c     f2838x_GlobalVariableDefs.obj (Dcc0RegsFile)

Dcc1RegsFile 
*          0    0005e740    0000002c     UNINITIALIZED
                  0005e740    0000002c     f2838x_GlobalVariableDefs.obj (Dcc1RegsFile)

Dcc2RegsFile 
*          0    0005e780    0000002c     UNINITIALIZED
                  0005e780    0000002c     f2838x_GlobalVariableDefs.obj (Dcc2RegsFile)

EradGlobalRegsFile 
*          0    0005e800    00000014     UNINITIALIZED
                  0005e800    00000014     f2838x_GlobalVariableDefs.obj (EradGlobalRegsFile)

EradHwbpRegsFile 
*          0    0005e900    00000008     UNINITIALIZED
                  0005e900    00000008     f2838x_GlobalVariableDefs.obj (EradHwbpRegsFile)

EradCounterRegsFile 
*          0    0005e980    0000000c     UNINITIALIZED
                  0005e980    0000000c     f2838x_GlobalVariableDefs.obj (EradCounterRegsFile)

EradCrcRegsFile 
*          0    0005ea00    00000006     UNINITIALIZED
                  0005ea00    00000006     f2838x_GlobalVariableDefs.obj (EradCrcRegsFile)

DcsmZ1RegsFile 
*          0    0005f000    0000003e     UNINITIALIZED
                  0005f000    0000003e     f2838x_GlobalVariableDefs.obj (DcsmZ1RegsFile)

DcsmZ2RegsFile 
*          0    0005f080    0000002c     UNINITIALIZED
                  0005f080    0000002c     f2838x_GlobalVariableDefs.obj (DcsmZ2RegsFile)

DcsmCommonRegsFile 
*          0    0005f0c0    0000001e     UNINITIALIZED
                  0005f0c0    0000001e     f2838x_GlobalVariableDefs.obj (DcsmCommonRegsFile)

MemCfgRegsFile 
*          0    0005f400    000000ae     UNINITIALIZED
                  0005f400    000000ae     f2838x_GlobalVariableDefs.obj (MemCfgRegsFile)

Emif1ConfigRegsFile 
*          0    0005f4c0    0000000a     UNINITIALIZED
                  0005f4c0    0000000a     f2838x_GlobalVariableDefs.obj (Emif1ConfigRegsFile)

Emif2ConfigRegsFile 
*          0    0005f4e0    0000000a     UNINITIALIZED
                  0005f4e0    0000000a     f2838x_GlobalVariableDefs.obj (Emif2ConfigRegsFile)

AccessProtectionRegsFile 
*          0    0005f500    0000002e     UNINITIALIZED
                  0005f500    0000002e     f2838x_GlobalVariableDefs.obj (AccessProtectionRegsFile)

MemoryErrorRegsFile 
*          0    0005f540    0000003a     UNINITIALIZED
                  0005f540    0000003a     f2838x_GlobalVariableDefs.obj (MemoryErrorRegsFile)

RomWaitStateRegsFile 
*          0    0005f580    00000002     UNINITIALIZED
                  0005f580    00000002     f2838x_GlobalVariableDefs.obj (RomWaitStateRegsFile)

RomPrefetchRegsFile 
*          0    0005f588    00000002     UNINITIALIZED
                  0005f588    00000002     f2838x_GlobalVariableDefs.obj (RomPrefetchRegsFile)

TestErrorRegsFile 
*          0    0005f590    00000006     UNINITIALIZED
                  0005f590    00000006     f2838x_GlobalVariableDefs.obj (TestErrorRegsFile)

Flash0CtrlRegsFile 
*          0    0005f800    00000182     UNINITIALIZED
                  0005f800    00000182     f2838x_GlobalVariableDefs.obj (Flash0CtrlRegsFile)

Flash0EccRegsFile 
*          0    0005fb00    00000028     UNINITIALIZED
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DcsmZ1OtpFile 
*          0    00078000    00000020     NOLOAD SECTION
                  00078000    00000020     f2838x_GlobalVariableDefs.obj (DcsmZ1OtpFile)

DcsmZ2OtpFile 
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.TI.ramfunc 
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PmbusaRegsFile 
*          0    00006400    0000001e     UNINITIALIZED
                  00006400    0000001e     f2838x_GlobalVariableDefs.obj (PmbusaRegsFile)

SciaRegsFile 
*          0    00007200    00000010     UNINITIALIZED
                  00007200    00000010     f2838x_GlobalVariableDefs.obj (SciaRegsFile)

ScibRegsFile 
*          0    00007210    00000010     UNINITIALIZED
                  00007210    00000010     f2838x_GlobalVariableDefs.obj (ScibRegsFile)

ScicRegsFile 
*          0    00007220    00000010     UNINITIALIZED
                  00007220    00000010     f2838x_GlobalVariableDefs.obj (ScicRegsFile)

ScidRegsFile 
*          0    00007230    00000010     UNINITIALIZED
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DmaClaSrcSelRegsFile 
*          0    00007980    0000001a     UNINITIALIZED
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DevCfgRegsFile 
*          0    0005d000    000001a0     UNINITIALIZED
                  0005d000    000001a0     f2838x_GlobalVariableDefs.obj (DevCfgRegsFile)

ClkCfgRegsFile 
*          0    0005d200    0000003a     UNINITIALIZED
                  0005d200    0000003a     f2838x_GlobalVariableDefs.obj (ClkCfgRegsFile)

CpuSysRegsFile 
*          0    0005d300    000000a0     UNINITIALIZED
                  0005d300    000000a0     f2838x_GlobalVariableDefs.obj (CpuSysRegsFile)

SysPeriphAcRegsFile 
*          0    0005d500    00000200     UNINITIALIZED
                  0005d500    00000200     f2838x_GlobalVariableDefs.obj (SysPeriphAcRegsFile)

CmConfRegsFile 
*          0    0005dc00    00000400     UNINITIALIZED
                  0005dc00    00000400     f2838x_GlobalVariableDefs.obj (CmConfRegsFile)

.text      0    00082000    000019a1     
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                  00082841    000003b9     Gpio.obj (.text:_InitGpio)
                  00082bfa    00000117     EPwm.obj (.text:_InitEPwm)
                  00082d11    000000f7     SysCtrl.obj (.text:_InitSysCtrl)
                  00082e08    000000b7     f2838x_adc.obj (.text:_AdcSetMode)
                  00082ebf    0000005f     Adc.obj (.text:_InitAdca)
                  00082f1e    00000056     rts2800_fpu32.lib : boot28.asm.obj (.text)
                  00082f74    0000003d     f2838x_adc.obj (.text:_CalAdcINL)
                  00082fb1    00000029     rts2800_fpu32.lib : exit.c.obj (.text)
                  00082fda    00000024                       : cpy_tbl.c.obj (.text)
                  00082ffe    00000022     f2838x_pievect.obj (.text:_InitPieVectTable)
                  00083020    0000001f     f2838x_piectrl.obj (.text:_InitPieCtrl)
                  0008303f    0000001d     Main.obj (.text:_main)
                  0008305c    0000001d     rts2800_fpu32.lib : memcpy.c.obj (.text)
                  00083079    00000012                       : args_main.c.obj (.text)
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                  000830b2    0000000d     f2838x_defaultisr.obj (.text:_CLB3_ISR)
                  000830bf    0000000d     f2838x_defaultisr.obj (.text:_CLB4_ISR)
                  000830cc    0000000d     f2838x_defaultisr.obj (.text:_CLB5_ISR)
                  000830d9    0000000d     f2838x_defaultisr.obj (.text:_CLB6_ISR)
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                  00083182    0000000d     f2838x_defaultisr.obj (.text:_ECATRSTINTN_ISR)
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                  000832a0    0000000d     f2838x_defaultisr.obj (.text:_FSIRXE1_ISR)
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                  000832ba    0000000d     f2838x_defaultisr.obj (.text:_FSIRXF1_ISR)
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                  000832d4    0000000d     f2838x_defaultisr.obj (.text:_FSIRXG1_ISR)
                  000832e1    0000000d     f2838x_defaultisr.obj (.text:_FSIRXG2_ISR)
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                  000832fb    0000000d     f2838x_defaultisr.obj (.text:_FSIRXH2_ISR)
                  00083308    0000000d     f2838x_defaultisr.obj (.text:_FSITXA1_ISR)
                  00083315    0000000d     f2838x_defaultisr.obj (.text:_FSITXA2_ISR)
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                  0008332f    0000000d     f2838x_defaultisr.obj (.text:_FSITXB2_ISR)
                  0008333c    0000000d     f2838x_defaultisr.obj (.text:_I2CA_HIGH_ISR)
                  00083349    0000000d     f2838x_defaultisr.obj (.text:_MCANSS0_ISR)
                  00083356    0000000d     f2838x_defaultisr.obj (.text:_MCANSS1_ISR)
                  00083363    0000000d     f2838x_defaultisr.obj (.text:_MCANSS_ECC_CORR_PLS_ISR)
                  00083370    0000000d     f2838x_defaultisr.obj (.text:_MCANSS_WAKE_AND_TS_PLS_ISR)
                  0008337d    0000000d     f2838x_defaultisr.obj (.text:_PBIST_ISR)
                  0008338a    0000000d     f2838x_defaultisr.obj (.text:_PMBUSA_ISR)
                  00083397    0000000d     EPwm.obj (.text:_PwmViennaOn)
                  000833a4    0000000d     f2838x_defaultisr.obj (.text:_SDFM1DR1_ISR)
                  000833b1    0000000d     f2838x_defaultisr.obj (.text:_SDFM1DR2_ISR)
                  000833be    0000000d     f2838x_defaultisr.obj (.text:_SDFM1DR3_ISR)
                  000833cb    0000000d     f2838x_defaultisr.obj (.text:_SDFM1DR4_ISR)
                  000833d8    0000000d     f2838x_defaultisr.obj (.text:_SDFM2DR1_ISR)
                  000833e5    0000000d     f2838x_defaultisr.obj (.text:_SDFM2DR2_ISR)
                  000833f2    0000000d     f2838x_defaultisr.obj (.text:_SDFM2DR3_ISR)
                  000833ff    0000000d     f2838x_defaultisr.obj (.text:_SDFM2DR4_ISR)
                  0008340c    0000000d     f2838x_defaultisr.obj (.text:_SPID_RX_ISR)
                  00083419    0000000d     f2838x_defaultisr.obj (.text:_SPID_TX_ISR)
                  00083426    0000000d     f2838x_defaultisr.obj (.text:_SYS_ERR_ISR)
                  00083433    0000000c     Watchdog.obj (.text:_InitWatchdog)
                  0008343f    0000000a     f2838x_defaultisr.obj (.text:_ADCA1_ISR)
                  00083449    0000000a     f2838x_defaultisr.obj (.text:_ADCA2_ISR)
                  00083453    0000000a     f2838x_defaultisr.obj (.text:_ADCA3_ISR)
                  0008345d    0000000a     f2838x_defaultisr.obj (.text:_ADCA4_ISR)
                  00083467    0000000a     f2838x_defaultisr.obj (.text:_ADCA_EVT_ISR)
                  00083471    0000000a     f2838x_defaultisr.obj (.text:_ADCB1_ISR)
                  0008347b    0000000a     f2838x_defaultisr.obj (.text:_ADCB2_ISR)
                  00083485    0000000a     f2838x_defaultisr.obj (.text:_ADCB3_ISR)
                  0008348f    0000000a     f2838x_defaultisr.obj (.text:_ADCB4_ISR)
                  00083499    0000000a     f2838x_defaultisr.obj (.text:_ADCB_EVT_ISR)
                  000834a3    0000000a     f2838x_defaultisr.obj (.text:_ADCC1_ISR)
                  000834ad    0000000a     f2838x_defaultisr.obj (.text:_ADCC2_ISR)
                  000834b7    0000000a     f2838x_defaultisr.obj (.text:_ADCC3_ISR)
                  000834c1    0000000a     f2838x_defaultisr.obj (.text:_ADCC4_ISR)
                  000834cb    0000000a     f2838x_defaultisr.obj (.text:_ADCC_EVT_ISR)
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                  000834e9    0000000a     f2838x_defaultisr.obj (.text:_ADCD3_ISR)
                  000834f3    0000000a     f2838x_defaultisr.obj (.text:_ADCD4_ISR)
                  000834fd    0000000a     f2838x_defaultisr.obj (.text:_ADCD_EVT_ISR)
                  00083507    0000000a     f2838x_defaultisr.obj (.text:_CANA0_ISR)
                  00083511    0000000a     f2838x_defaultisr.obj (.text:_CANA1_ISR)
                  0008351b    0000000a     f2838x_defaultisr.obj (.text:_CANB0_ISR)
                  00083525    0000000a     f2838x_defaultisr.obj (.text:_CANB1_ISR)
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                  00083539    0000000a     f2838x_defaultisr.obj (.text:_CIPC1_ISR)
                  00083543    0000000a     f2838x_defaultisr.obj (.text:_CIPC2_ISR)
                  0008354d    0000000a     f2838x_defaultisr.obj (.text:_CIPC3_ISR)
                  00083557    0000000a     f2838x_defaultisr.obj (.text:_CLA1_1_ISR)
                  00083561    0000000a     f2838x_defaultisr.obj (.text:_CLA1_2_ISR)
                  0008356b    0000000a     f2838x_defaultisr.obj (.text:_CLA1_3_ISR)
                  00083575    0000000a     f2838x_defaultisr.obj (.text:_CLA1_4_ISR)
                  0008357f    0000000a     f2838x_defaultisr.obj (.text:_CLA1_5_ISR)
                  00083589    0000000a     f2838x_defaultisr.obj (.text:_CLA1_6_ISR)
                  00083593    0000000a     f2838x_defaultisr.obj (.text:_CLA1_7_ISR)
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                  000835a7    0000000a     f2838x_defaultisr.obj (.text:_CLA_OVERFLOW_ISR)
                  000835b1    0000000a     f2838x_defaultisr.obj (.text:_CLA_UNDERFLOW_ISR)
                  000835bb    0000000a     f2838x_defaultisr.obj (.text:_DATALOG_ISR)
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                  000835cf    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH2_ISR)
                  000835d9    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH3_ISR)
                  000835e3    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH4_ISR)
                  000835ed    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH5_ISR)
                  000835f7    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH6_ISR)
                  00083601    0000000a     f2838x_defaultisr.obj (.text:_ECAP1_ISR)
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                  00083615    0000000a     f2838x_defaultisr.obj (.text:_ECAP3_ISR)
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                  00083629    0000000a     f2838x_defaultisr.obj (.text:_ECAP5_ISR)
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                  00083665    0000000a     f2838x_defaultisr.obj (.text:_EMU_ISR)
                  0008366f    0000000a     f2838x_defaultisr.obj (.text:_EPWM10_ISR)
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                  0008368d    0000000a     f2838x_defaultisr.obj (.text:_EPWM11_TZ_ISR)
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                  000836a1    0000000a     f2838x_defaultisr.obj (.text:_EPWM12_TZ_ISR)
                  000836ab    0000000a     f2838x_defaultisr.obj (.text:_EPWM1_TZ_ISR)
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                  000836bf    0000000a     f2838x_defaultisr.obj (.text:_EPWM2_TZ_ISR)
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                  000836e7    0000000a     f2838x_defaultisr.obj (.text:_EPWM4_TZ_ISR)
                  000836f1    0000000a     f2838x_defaultisr.obj (.text:_EPWM5_ISR)
                  000836fb    0000000a     f2838x_defaultisr.obj (.text:_EPWM5_TZ_ISR)
                  00083705    0000000a     f2838x_defaultisr.obj (.text:_EPWM6_ISR)
                  0008370f    0000000a     f2838x_defaultisr.obj (.text:_EPWM6_TZ_ISR)
                  00083719    0000000a     f2838x_defaultisr.obj (.text:_EPWM7_ISR)
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                  0008372d    0000000a     f2838x_defaultisr.obj (.text:_EPWM8_ISR)
                  00083737    0000000a     f2838x_defaultisr.obj (.text:_EPWM8_TZ_ISR)
                  00083741    0000000a     f2838x_defaultisr.obj (.text:_EPWM9_ISR)
                  0008374b    0000000a     f2838x_defaultisr.obj (.text:_EPWM9_TZ_ISR)
                  00083755    0000000a     f2838x_defaultisr.obj (.text:_EQEP1_ISR)
                  0008375f    0000000a     f2838x_defaultisr.obj (.text:_EQEP2_ISR)
                  00083769    0000000a     f2838x_defaultisr.obj (.text:_EQEP3_ISR)
                  00083773    0000000a     f2838x_defaultisr.obj (.text:_FPU_OFLOW_ISR)
                  0008377d    0000000a     f2838x_defaultisr.obj (.text:_FPU_UFLOW_ISR)
                  00083787    0000000a     f2838x_defaultisr.obj (.text:_I2CA_FIFO_ISR)
                  00083791    0000000a     f2838x_defaultisr.obj (.text:_I2CA_ISR)
                  0008379b    0000000a     f2838x_defaultisr.obj (.text:_I2CB_FIFO_ISR)
                  000837a5    0000000a     f2838x_defaultisr.obj (.text:_I2CB_ISR)
                  000837af    0000000a     f2838x_defaultisr.obj (.text:_ILLEGAL_ISR)
                  000837b9    0000000a     f2838x_defaultisr.obj (.text:_MCBSPA_RX_ISR)
                  000837c3    0000000a     f2838x_defaultisr.obj (.text:_MCBSPA_TX_ISR)
                  000837cd    0000000a     f2838x_defaultisr.obj (.text:_MCBSPB_RX_ISR)
                  000837d7    0000000a     f2838x_defaultisr.obj (.text:_MCBSPB_TX_ISR)
                  000837e1    0000000a     f2838x_defaultisr.obj (.text:_NMI_ISR)
                  000837eb    0000000a     f2838x_defaultisr.obj (.text:_NOTUSED_ISR)
                  000837f5    0000000a     f2838x_defaultisr.obj (.text:_PIE_RESERVED_ISR)
                  000837ff    0000000a     f2838x_defaultisr.obj (.text:_RTOS_ISR)
                  00083809    0000000a     f2838x_defaultisr.obj (.text:_SCIA_RX_ISR)
                  00083813    0000000a     f2838x_defaultisr.obj (.text:_SCIA_TX_ISR)
                  0008381d    0000000a     f2838x_defaultisr.obj (.text:_SCIB_RX_ISR)
                  00083827    0000000a     f2838x_defaultisr.obj (.text:_SCIB_TX_ISR)
                  00083831    0000000a     f2838x_defaultisr.obj (.text:_SCIC_RX_ISR)
                  0008383b    0000000a     f2838x_defaultisr.obj (.text:_SCIC_TX_ISR)
                  00083845    0000000a     f2838x_defaultisr.obj (.text:_SCID_RX_ISR)
                  0008384f    0000000a     f2838x_defaultisr.obj (.text:_SCID_TX_ISR)
                  00083859    0000000a     f2838x_defaultisr.obj (.text:_SDFM1_ISR)
                  00083863    0000000a     f2838x_defaultisr.obj (.text:_SDFM2_ISR)
                  0008386d    0000000a     f2838x_defaultisr.obj (.text:_SPIA_RX_ISR)
                  00083877    0000000a     f2838x_defaultisr.obj (.text:_SPIA_TX_ISR)
                  00083881    0000000a     f2838x_defaultisr.obj (.text:_SPIB_RX_ISR)
                  0008388b    0000000a     f2838x_defaultisr.obj (.text:_SPIB_TX_ISR)
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                  000838a9    0000000a     f2838x_defaultisr.obj (.text:_TIMER0_ISR)
                  000838b3    0000000a     f2838x_defaultisr.obj (.text:_TIMER1_ISR)
                  000838bd    0000000a     f2838x_defaultisr.obj (.text:_TIMER2_ISR)
                  000838c7    0000000a     f2838x_defaultisr.obj (.text:_USBA_ISR)
                  000838d1    0000000a     f2838x_defaultisr.obj (.text:_USER10_ISR)
                  000838db    0000000a     f2838x_defaultisr.obj (.text:_USER11_ISR)
                  000838e5    0000000a     f2838x_defaultisr.obj (.text:_USER12_ISR)
                  000838ef    0000000a     f2838x_defaultisr.obj (.text:_USER1_ISR)
                  000838f9    0000000a     f2838x_defaultisr.obj (.text:_USER2_ISR)
                  00083903    0000000a     f2838x_defaultisr.obj (.text:_USER3_ISR)
                  0008390d    0000000a     f2838x_defaultisr.obj (.text:_USER4_ISR)
                  00083917    0000000a     f2838x_defaultisr.obj (.text:_USER5_ISR)
                  00083921    0000000a     f2838x_defaultisr.obj (.text:_USER6_ISR)
                  0008392b    0000000a     f2838x_defaultisr.obj (.text:_USER7_ISR)
                  00083935    0000000a     f2838x_defaultisr.obj (.text:_USER8_ISR)
                  0008393f    0000000a     f2838x_defaultisr.obj (.text:_USER9_ISR)
                  00083949    0000000a     f2838x_defaultisr.obj (.text:_WAKE_ISR)
                  00083953    0000000a     f2838x_defaultisr.obj (.text:_XINT1_ISR)
                  0008395d    0000000a     f2838x_defaultisr.obj (.text:_XINT2_ISR)
                  00083967    0000000a     f2838x_defaultisr.obj (.text:_XINT3_ISR)
                  00083971    0000000a     f2838x_defaultisr.obj (.text:_XINT4_ISR)
                  0008397b    0000000a     f2838x_defaultisr.obj (.text:_XINT5_ISR)
                  00083985    00000009     f2838x_piectrl.obj (.text:_EnableInterrupts)
                  0008398e    00000009     rts2800_fpu32.lib : _lock.c.obj (.text)
                  00083997    00000007     SetInterrupts.obj (.text:_SetInterrupts)
                  0008399e    00000002     rts2800_fpu32.lib : pre_init.c.obj (.text)
                  000839a0    00000001                       : startup.c.obj (.text)

.econst    0    0008801c    000001c0     
                  0008801c    000001c0     f2838x_pievect.obj (.econst:_PieVectTableInit)

MODULE SUMMARY

       Module                            code   initialized data   uninitialized data
       ------                            ----   ----------------   ------------------
    .\
       f2838x_GlobalVariableDefs.obj     0      0                  13199             
       f2838x_defaultisr.obj             2273   0                  0                 
       Xbar.obj                          2113   0                  0                 
       Gpio.obj                          953    0                  0                 
       f2838x_pievect.obj                34     448                0                 
       EPwm.obj                          292    0                  0                 
       SysCtrl.obj                       247    0                  0                 
       f2838x_adc.obj                    244    0                  0                 
       Adc.obj                           95     0                  0                 
       f2838x_piectrl.obj                40     0                  0                 
       interrupt_EPwm1_latency_isr.obj   32     0                  0                 
       Main.obj                          29     0                  0                 
       Watchdog.obj                      12     0                  0                 
       SetInterrupts.obj                 7      0                  0                 
       F2838x_CodeStartBranch.obj        2      0                  0                 
    +--+---------------------------------+------+------------------+--------------------+
       Total:                            6373   448                13199             
                                                                                     
    C:\ti\ccs920\ccs\tools\compiler\ti-cgt-C2000_21.6.0.LTS\lib\rts2800_fpu32.lib
       boot28.asm.obj                    86     0                  0                 
       exit.c.obj                        41     14                 6                 
       cpy_tbl.c.obj                     36     0                  0                 
       memcpy.c.obj                      29     0                  0                 
       _lock.c.obj                       9      10                 4                 
       args_main.c.obj                   18     0                  0                 
       pre_init.c.obj                    2      0                  0                 
       startup.c.obj                     1      0                  0                 
    +--+---------------------------------+------+------------------+--------------------+
       Total:                            222    24                 10                
                                                                                     
       Stack:                            0      0                  512               
    +--+---------------------------------+------+------------------+--------------------+
       Grand Total:                      6595   472                13721             


GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE

address     data page           name
--------    ----------------    ----
00000400      10 (00000400)     __stack

00000b00      2c (00000b00)     _AdcaResultRegs
00000b20      2c (00000b00)     _AdcbResultRegs

00000b40      2d (00000b40)     _AdccResultRegs
00000b60      2d (00000b40)     _AdcdResultRegs

00000c00      30 (00000c00)     _CpuTimer0Regs
00000c08      30 (00000c00)     _CpuTimer1Regs
00000c10      30 (00000c00)     _CpuTimer2Regs

00000ce0      33 (00000cc0)     _PieCtrlRegs

00000d00      34 (00000d00)     _EmuBMode
00000d00      34 (00000d00)     _PieVectTable
00000d01      34 (00000d00)     _EmuBootPins

00001000      40 (00001000)     _DmaRegs

00001400      50 (00001400)     _Cla1Regs

00004000     100 (00004000)     _EPwm1Regs

00004100     104 (00004100)     _EPwm2Regs

00004200     108 (00004200)     _EPwm3Regs

00004300     10c (00004300)     _EPwm4Regs

00004400     110 (00004400)     _EPwm5Regs

00004500     114 (00004500)     _EPwm6Regs

00004600     118 (00004600)     _EPwm7Regs

00004700     11c (00004700)     _EPwm8Regs

00004800     120 (00004800)     _EPwm9Regs

00004900     124 (00004900)     _EPwm10Regs

00004a00     128 (00004a00)     _EPwm11Regs

00004b00     12c (00004b00)     _EPwm12Regs

00004c00     130 (00004c00)     _EPwm13Regs

00004d00     134 (00004d00)     _EPwm14Regs

00004e00     138 (00004e00)     _EPwm15Regs

00004f00     13c (00004f00)     _EPwm16Regs

00005100     144 (00005100)     _EQep1Regs

00005140     145 (00005140)     _EQep2Regs

00005180     146 (00005180)     _EQep3Regs

00005200     148 (00005200)     _ECap1Regs

00005240     149 (00005240)     _ECap2Regs

00005280     14a (00005280)     _ECap3Regs

000052c0     14b (000052c0)     _ECap4Regs

00005300     14c (00005300)     _ECap5Regs

00005340     14d (00005340)     _ECap6Regs
00005360     14d (00005340)     _HRCap6Regs

00005380     14e (00005380)     _ECap7Regs
000053a0     14e (00005380)     _HRCap7Regs

00005c00     170 (00005c00)     _DacaRegs
00005c10     170 (00005c00)     _DacbRegs
00005c20     170 (00005c00)     _DaccRegs

00005c80     172 (00005c80)     _Cmpss1Regs
00005ca0     172 (00005c80)     _Cmpss2Regs

00005cc0     173 (00005cc0)     _Cmpss3Regs
00005ce0     173 (00005cc0)     _Cmpss4Regs

00005d00     174 (00005d00)     _Cmpss5Regs
00005d20     174 (00005d00)     _Cmpss6Regs

00005d40     175 (00005d40)     _Cmpss7Regs
00005d60     175 (00005d40)     _Cmpss8Regs

00005e00     178 (00005e00)     _Sdfm1Regs

00005e80     17a (00005e80)     _Sdfm2Regs

00006000     180 (00006000)     _McbspaRegs

00006040     181 (00006040)     _McbspbRegs

00006100     184 (00006100)     _SpiaRegs
00006110     184 (00006100)     _SpibRegs
00006120     184 (00006100)     _SpicRegs
00006130     184 (00006100)     _SpidRegs

00006340     18d (00006340)     _BgcrcCpuRegs

00006380     18e (00006380)     _BgcrcCla1Regs

00006400     190 (00006400)     _PmbusaRegs

00006600     198 (00006600)     _FsiTxaRegs

00006680     19a (00006680)     _FsiRxaRegs

00006700     19c (00006700)     _FsiTxbRegs

00006780     19e (00006780)     _FsiRxbRegs

00006880     1a2 (00006880)     _FsiRxcRegs

00006980     1a6 (00006980)     _FsiRxdRegs

00006a80     1aa (00006a80)     _FsiRxeRegs

00006b80     1ae (00006b80)     _FsiRxfRegs

00006c80     1b2 (00006c80)     _FsiRxgRegs

00006d80     1b6 (00006d80)     _FsiRxhRegs

00007000     1c0 (00007000)     _WdRegs

00007060     1c1 (00007040)     _NmiIntruptRegs
00007070     1c1 (00007040)     _XintRegs

00007200     1c8 (00007200)     _SciaRegs
00007210     1c8 (00007200)     _ScibRegs
00007220     1c8 (00007200)     _ScicRegs
00007230     1c8 (00007200)     _ScidRegs

00007300     1cc (00007300)     _I2caRegs

00007340     1cd (00007340)     _I2cbRegs

00007400     1d0 (00007400)     _AdcaRegs

00007480     1d2 (00007480)     _AdcbRegs

00007500     1d4 (00007500)     _AdccRegs

00007580     1d6 (00007580)     _AdcdRegs

00007900     1e4 (00007900)     _InputXbarRegs
00007920     1e4 (00007900)     _XbarRegs

00007940     1e5 (00007940)     _SyncSocRegs

00007980     1e6 (00007980)     _DmaClaSrcSelRegs

00007a00     1e8 (00007a00)     _EPwmXbarRegs

00007a80     1ea (00007a80)     _OutputXbarRegs

00007c00     1f0 (00007c00)     _GpioCtrlRegs

00007f00     1fc (00007f00)     _GpioDataRegs

0000a800     2a0 (0000a800)     ___TI_enable_exit_profile_output
0000a802     2a0 (0000a800)     ___TI_cleanup_ptr
0000a804     2a0 (0000a800)     ___TI_dtors_ptr
0000a806     2a0 (0000a800)     __lock
0000a808     2a0 (0000a800)     __unlock

00047000    11c0 (00047000)     _Emif1Regs

00047800    11e0 (00047800)     _Emif2Regs

00048000    1200 (00048000)     _CanaRegs

0004a000    1280 (0004a000)     _CanbRegs

00057e00    15f8 (00057e00)     _EcatssRegs

00057f00    15fc (00057f00)     _EcatssConfigRegs

0005c400    1710 (0005c400)     _McanssRegs

0005c600    1718 (0005c600)     _McanRegs

0005c800    1720 (0005c800)     _McanErrorRegs

0005ce00    1738 (0005ce00)     _Cpu1toCpu2IpcRegs

0005ce40    1739 (0005ce40)     _Cpu1toCmIpcRegs

0005d000    1740 (0005d000)     _DevCfgRegs

0005d200    1748 (0005d200)     _ClkCfgRegs

0005d300    174c (0005d300)     _CpuSysRegs

0005d400    1750 (0005d400)     _SysStatusRegs

0005d500    1754 (0005d500)     _SysPeriphAcRegs

0005d700    175c (0005d700)     _AnalogSubsysRegs

0005dc00    1770 (0005dc00)     _CmConfRegs

0005e000    1780 (0005e000)     _HwbistRegs

0005e700    179c (0005e700)     _Dcc0Regs

0005e740    179d (0005e740)     _Dcc1Regs

0005e780    179e (0005e780)     _Dcc2Regs

0005e800    17a0 (0005e800)     _EradGlobalRegs

0005e900    17a4 (0005e900)     _EradHwbpRegs

0005e980    17a6 (0005e980)     _EradCounterRegs

0005ea00    17a8 (0005ea00)     _EradCrcRegs

0005f000    17c0 (0005f000)     _DcsmZ1Regs

0005f080    17c2 (0005f080)     _DcsmZ2Regs

0005f0c0    17c3 (0005f0c0)     _DcsmCommonRegs

0005f400    17d0 (0005f400)     _MemCfgRegs

0005f4c0    17d3 (0005f4c0)     _Emif1ConfigRegs
0005f4e0    17d3 (0005f4c0)     _Emif2ConfigRegs

0005f500    17d4 (0005f500)     _AccessProtectionRegs

0005f540    17d5 (0005f540)     _MemoryErrorRegs

0005f580    17d6 (0005f580)     _RomWaitStateRegs
0005f588    17d6 (0005f580)     _RomPrefetchRegs
0005f590    17d6 (0005f580)     _TestErrorRegs

0005f800    17e0 (0005f800)     _Flash0CtrlRegs

0005fb00    17ec (0005fb00)     _Flash0EccRegs

00078000    1e00 (00078000)     _DcsmZ1Otp

00078200    1e08 (00078200)     _DcsmZ2Otp

0008801c    2200 (00088000)     _PieVectTableInit


GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name 

page  address   name                            
----  -------   ----                            
abs   ffffffff  .text                           
0     00082fb1  C$$EXIT                         
0     0008343f  _ADCA1_ISR                      
0     00083449  _ADCA2_ISR                      
0     00083453  _ADCA3_ISR                      
0     0008345d  _ADCA4_ISR                      
0     00083467  _ADCA_EVT_ISR                   
0     00083471  _ADCB1_ISR                      
0     0008347b  _ADCB2_ISR                      
0     00083485  _ADCB3_ISR                      
0     0008348f  _ADCB4_ISR                      
0     00083499  _ADCB_EVT_ISR                   
0     000834a3  _ADCC1_ISR                      
0     000834ad  _ADCC2_ISR                      
0     000834b7  _ADCC3_ISR                      
0     000834c1  _ADCC4_ISR                      
0     000834cb  _ADCC_EVT_ISR                   
0     000834d5  _ADCD1_ISR                      
0     000834df  _ADCD2_ISR                      
0     000834e9  _ADCD3_ISR                      
0     000834f3  _ADCD4_ISR                      
0     000834fd  _ADCD_EVT_ISR                   
0     0005f500  _AccessProtectionRegs           
0     00082e08  _AdcSetMode                     
0     00007400  _AdcaRegs                       
0     00000b00  _AdcaResultRegs                 
0     00007480  _AdcbRegs                       
0     00000b20  _AdcbResultRegs                 
0     00007500  _AdccRegs                       
0     00000b40  _AdccResultRegs                 
0     00007580  _AdcdRegs                       
0     00000b60  _AdcdResultRegs                 
0     0005d700  _AnalogSubsysRegs               
0     00006380  _BgcrcCla1Regs                  
0     00006340  _BgcrcCpuRegs                   
0     00083507  _CANA0_ISR                      
0     00083511  _CANA1_ISR                      
0     0008351b  _CANB0_ISR                      
0     00083525  _CANB1_ISR                      
0     0008352f  _CIPC0_ISR                      
0     00083539  _CIPC1_ISR                      
0     00083543  _CIPC2_ISR                      
0     0008354d  _CIPC3_ISR                      
0     0008308b  _CLA1CRC_INT_ISR                
0     00083557  _CLA1_1_ISR                     
0     00083561  _CLA1_2_ISR                     
0     0008356b  _CLA1_3_ISR                     
0     00083575  _CLA1_4_ISR                     
0     0008357f  _CLA1_5_ISR                     
0     00083589  _CLA1_6_ISR                     
0     00083593  _CLA1_7_ISR                     
0     0008359d  _CLA1_8_ISR                     
0     000835a7  _CLA_OVERFLOW_ISR               
0     000835b1  _CLA_UNDERFLOW_ISR              
0     00083098  _CLB1_ISR                       
0     000830a5  _CLB2_ISR                       
0     000830b2  _CLB3_ISR                       
0     000830bf  _CLB4_ISR                       
0     000830cc  _CLB5_ISR                       
0     000830d9  _CLB6_ISR                       
0     000830e6  _CLB7_ISR                       
0     000830f3  _CLB8_ISR                       
0     00083100  _CMTOCPUXIPC0_ISR               
0     0008310d  _CMTOCPUXIPC1_ISR               
0     0008311a  _CMTOCPUXIPC2_ISR               
0     00083127  _CMTOCPUXIPC3_ISR               
0     00083134  _CMTOCPUXIPC4_ISR               
0     00083141  _CMTOCPUXIPC5_ISR               
0     0008314e  _CMTOCPUXIPC6_ISR               
0     0008315b  _CMTOCPUXIPC7_ISR               
0     00083168  _CM_STATUS_ISR                  
0     00083175  _CPUCRC_INT_ISR                 
0     00082f74  _CalAdcINL                      
0     00048000  _CanaRegs                       
0     0004a000  _CanbRegs                       
0     00001400  _Cla1Regs                       
0     0005d200  _ClkCfgRegs                     
0     0005dc00  _CmConfRegs                     
0     00005c80  _Cmpss1Regs                     
0     00005ca0  _Cmpss2Regs                     
0     00005cc0  _Cmpss3Regs                     
0     00005ce0  _Cmpss4Regs                     
0     00005d00  _Cmpss5Regs                     
0     00005d20  _Cmpss6Regs                     
0     00005d40  _Cmpss7Regs                     
0     00005d60  _Cmpss8Regs                     
0     0005ce40  _Cpu1toCmIpcRegs                
0     0005ce00  _Cpu1toCpu2IpcRegs              
0     0005d300  _CpuSysRegs                     
0     00000c00  _CpuTimer0Regs                  
0     00000c08  _CpuTimer1Regs                  
0     00000c10  _CpuTimer2Regs                  
0     000835bb  _DATALOG_ISR                    
0     000835c5  _DMA_CH1_ISR                    
0     000835cf  _DMA_CH2_ISR                    
0     000835d9  _DMA_CH3_ISR                    
0     000835e3  _DMA_CH4_ISR                    
0     000835ed  _DMA_CH5_ISR                    
0     000835f7  _DMA_CH6_ISR                    
0     00005c00  _DacaRegs                       
0     00005c10  _DacbRegs                       
0     00005c20  _DaccRegs                       
0     0005e700  _Dcc0Regs                       
0     0005e740  _Dcc1Regs                       
0     0005e780  _Dcc2Regs                       
0     0005f0c0  _DcsmCommonRegs                 
0     00078000  _DcsmZ1Otp                      
0     0005f000  _DcsmZ1Regs                     
0     00078200  _DcsmZ2Otp                      
0     0005f080  _DcsmZ2Regs                     
0     0005d000  _DevCfgRegs                     
0     00007980  _DmaClaSrcSelRegs               
0     00001000  _DmaRegs                        
0     00083601  _ECAP1_ISR                      
0     0008360b  _ECAP2_ISR                      
0     00083615  _ECAP3_ISR                      
0     0008361f  _ECAP4_ISR                      
0     00083629  _ECAP5_ISR                      
0     00083633  _ECAP6_2_ISR                    
0     0008363d  _ECAP6_ISR                      
0     00083647  _ECAP7_2_ISR                    
0     00083651  _ECAP7_ISR                      
0     00083182  _ECATRSTINTN_ISR                
0     0008318f  _ECATSYNC0_ISR                  
0     0008319c  _ECATSYNC1_ISR                  
0     000831a9  _ECAT_ISR                       
0     00005200  _ECap1Regs                      
0     00005240  _ECap2Regs                      
0     00005280  _ECap3Regs                      
0     000052c0  _ECap4Regs                      
0     00005300  _ECap5Regs                      
0     00005340  _ECap6Regs                      
0     00005380  _ECap7Regs                      
0     0008365b  _EMIF_ERROR_ISR                 
0     000831b6  _EMPTY_ISR                      
0     00083665  _EMU_ISR                        
0     0008366f  _EPWM10_ISR                     
0     00083679  _EPWM10_TZ_ISR                  
0     00083683  _EPWM11_ISR                     
0     0008368d  _EPWM11_TZ_ISR                  
0     00083697  _EPWM12_ISR                     
0     000836a1  _EPWM12_TZ_ISR                  
0     000831c3  _EPWM13_ISR                     
0     000831d0  _EPWM13_TZ_ISR                  
0     000831dd  _EPWM14_ISR                     
0     000831ea  _EPWM14_TZ_ISR                  
0     000831f7  _EPWM15_ISR                     
0     00083204  _EPWM15_TZ_ISR                  
0     00083211  _EPWM16_ISR                     
0     0008321e  _EPWM16_TZ_ISR                  
0     00008000  _EPWM1_ISR                      
0     000836ab  _EPWM1_TZ_ISR                   
0     000836b5  _EPWM2_ISR                      
0     000836bf  _EPWM2_TZ_ISR                   
0     000836c9  _EPWM3_ISR                      
0     000836d3  _EPWM3_TZ_ISR                   
0     000836dd  _EPWM4_ISR                      
0     000836e7  _EPWM4_TZ_ISR                   
0     000836f1  _EPWM5_ISR                      
0     000836fb  _EPWM5_TZ_ISR                   
0     00083705  _EPWM6_ISR                      
0     0008370f  _EPWM6_TZ_ISR                   
0     00083719  _EPWM7_ISR                      
0     00083723  _EPWM7_TZ_ISR                   
0     0008372d  _EPWM8_ISR                      
0     00083737  _EPWM8_TZ_ISR                   
0     00083741  _EPWM9_ISR                      
0     0008374b  _EPWM9_TZ_ISR                   
0     00004900  _EPwm10Regs                     
0     00004a00  _EPwm11Regs                     
0     00004b00  _EPwm12Regs                     
0     00004c00  _EPwm13Regs                     
0     00004d00  _EPwm14Regs                     
0     00004e00  _EPwm15Regs                     
0     00004f00  _EPwm16Regs                     
0     00004000  _EPwm1Regs                      
0     00004100  _EPwm2Regs                      
0     00004200  _EPwm3Regs                      
0     00004300  _EPwm4Regs                      
0     00004400  _EPwm5Regs                      
0     00004500  _EPwm6Regs                      
0     00004600  _EPwm7Regs                      
0     00004700  _EPwm8Regs                      
0     00004800  _EPwm9Regs                      
0     00007a00  _EPwmXbarRegs                   
0     00083755  _EQEP1_ISR                      
0     0008375f  _EQEP2_ISR                      
0     00083769  _EQEP3_ISR                      
0     00005100  _EQep1Regs                      
0     00005140  _EQep2Regs                      
0     00005180  _EQep3Regs                      
0     00057f00  _EcatssConfigRegs               
0     00057e00  _EcatssRegs                     
0     0005f4c0  _Emif1ConfigRegs                
0     00047000  _Emif1Regs                      
0     0005f4e0  _Emif2ConfigRegs                
0     00047800  _Emif2Regs                      
0     00000d00  _EmuBMode                       
0     00000d01  _EmuBootPins                    
0     00083985  _EnableInterrupts               
0     0005e980  _EradCounterRegs                
0     0005ea00  _EradCrcRegs                    
0     0005e800  _EradGlobalRegs                 
0     0005e900  _EradHwbpRegs                   
0     0008322b  _FMC_ISR                        
0     00083773  _FPU_OFLOW_ISR                  
0     0008377d  _FPU_UFLOW_ISR                  
0     00083238  _FSIRXA1_ISR                    
0     00083245  _FSIRXA2_ISR                    
0     00083252  _FSIRXB1_ISR                    
0     0008325f  _FSIRXB2_ISR                    
0     0008326c  _FSIRXC1_ISR                    
0     00083279  _FSIRXC2_ISR                    
0     00083286  _FSIRXD1_ISR                    
0     00083293  _FSIRXD2_ISR                    
0     000832a0  _FSIRXE1_ISR                    
0     000832ad  _FSIRXE2_ISR                    
0     000832ba  _FSIRXF1_ISR                    
0     000832c7  _FSIRXF2_ISR                    
0     000832d4  _FSIRXG1_ISR                    
0     000832e1  _FSIRXG2_ISR                    
0     000832ee  _FSIRXH1_ISR                    
0     000832fb  _FSIRXH2_ISR                    
0     00083308  _FSITXA1_ISR                    
0     00083315  _FSITXA2_ISR                    
0     00083322  _FSITXB1_ISR                    
0     0008332f  _FSITXB2_ISR                    
0     0005f800  _Flash0CtrlRegs                 
0     0005fb00  _Flash0EccRegs                  
0     00006680  _FsiRxaRegs                     
0     00006780  _FsiRxbRegs                     
0     00006880  _FsiRxcRegs                     
0     00006980  _FsiRxdRegs                     
0     00006a80  _FsiRxeRegs                     
0     00006b80  _FsiRxfRegs                     
0     00006c80  _FsiRxgRegs                     
0     00006d80  _FsiRxhRegs                     
0     00006600  _FsiTxaRegs                     
0     00006700  _FsiTxbRegs                     
0     00007c00  _GpioCtrlRegs                   
0     00007f00  _GpioDataRegs                   
0     00005360  _HRCap6Regs                     
0     000053a0  _HRCap7Regs                     
0     0005e000  _HwbistRegs                     
0     00083787  _I2CA_FIFO_ISR                  
0     0008333c  _I2CA_HIGH_ISR                  
0     00083791  _I2CA_ISR                       
0     0008379b  _I2CB_FIFO_ISR                  
0     000837a5  _I2CB_ISR                       
0     00007300  _I2caRegs                       
0     00007340  _I2cbRegs                       
0     000837af  _ILLEGAL_ISR                    
0     00082ebf  _InitAdca                       
0     00082bfa  _InitEPwm                       
0     00082841  _InitGpio                       
0     00083020  _InitPieCtrl                    
0     00082ffe  _InitPieVectTable               
0     00082d11  _InitSysCtrl                    
0     00083433  _InitWatchdog                   
0     00082000  _InitXbar                       
0     00007900  _InputXbarRegs                  
0     00083349  _MCANSS0_ISR                    
0     00083356  _MCANSS1_ISR                    
0     00083363  _MCANSS_ECC_CORR_PLS_ISR        
0     00083370  _MCANSS_WAKE_AND_TS_PLS_ISR     
0     000837b9  _MCBSPA_RX_ISR                  
0     000837c3  _MCBSPA_TX_ISR                  
0     000837cd  _MCBSPB_RX_ISR                  
0     000837d7  _MCBSPB_TX_ISR                  
0     0005c800  _McanErrorRegs                  
0     0005c600  _McanRegs                       
0     0005c400  _McanssRegs                     
0     00006000  _McbspaRegs                     
0     00006040  _McbspbRegs                     
0     0005f400  _MemCfgRegs                     
0     0005f540  _MemoryErrorRegs                
0     000837e1  _NMI_ISR                        
0     000837eb  _NOTUSED_ISR                    
0     00007060  _NmiIntruptRegs                 
0     00007a80  _OutputXbarRegs                 
0     0008337d  _PBIST_ISR                      
0     000837f5  _PIE_RESERVED_ISR               
0     0008338a  _PMBUSA_ISR                     
0     00000ce0  _PieCtrlRegs                    
0     00000d00  _PieVectTable                   
0     0008801c  _PieVectTableInit               
0     00006400  _PmbusaRegs                     
0     00083397  _PwmViennaOn                    
0     000837ff  _RTOS_ISR                       
0     00086010  _RamfuncsLoadEnd                
abs   00000010  _RamfuncsLoadSize               
0     00086000  _RamfuncsLoadStart              
0     00008010  _RamfuncsRunEnd                 
abs   00000010  _RamfuncsRunSize                
0     00008000  _RamfuncsRunStart               
0     0005f588  _RomPrefetchRegs                
0     0005f580  _RomWaitStateRegs               
0     00083809  _SCIA_RX_ISR                    
0     00083813  _SCIA_TX_ISR                    
0     0008381d  _SCIB_RX_ISR                    
0     00083827  _SCIB_TX_ISR                    
0     00083831  _SCIC_RX_ISR                    
0     0008383b  _SCIC_TX_ISR                    
0     00083845  _SCID_RX_ISR                    
0     0008384f  _SCID_TX_ISR                    
0     000833a4  _SDFM1DR1_ISR                   
0     000833b1  _SDFM1DR2_ISR                   
0     000833be  _SDFM1DR3_ISR                   
0     000833cb  _SDFM1DR4_ISR                   
0     00083859  _SDFM1_ISR                      
0     000833d8  _SDFM2DR1_ISR                   
0     000833e5  _SDFM2DR2_ISR                   
0     000833f2  _SDFM2DR3_ISR                   
0     000833ff  _SDFM2DR4_ISR                   
0     00083863  _SDFM2_ISR                      
0     0008386d  _SPIA_RX_ISR                    
0     00083877  _SPIA_TX_ISR                    
0     00083881  _SPIB_RX_ISR                    
0     0008388b  _SPIB_TX_ISR                    
0     00083895  _SPIC_RX_ISR                    
0     0008389f  _SPIC_TX_ISR                    
0     0008340c  _SPID_RX_ISR                    
0     00083419  _SPID_TX_ISR                    
0     00083426  _SYS_ERR_ISR                    
0     00007200  _SciaRegs                       
0     00007210  _ScibRegs                       
0     00007220  _ScicRegs                       
0     00007230  _ScidRegs                       
0     00005e00  _Sdfm1Regs                      
0     00005e80  _Sdfm2Regs                      
0     00083997  _SetInterrupts                  
0     00006100  _SpiaRegs                       
0     00006110  _SpibRegs                       
0     00006120  _SpicRegs                       
0     00006130  _SpidRegs                       
0     00007940  _SyncSocRegs                    
0     0005d500  _SysPeriphAcRegs                
0     0005d400  _SysStatusRegs                  
0     000838a9  _TIMER0_ISR                     
0     000838b3  _TIMER1_ISR                     
0     000838bd  _TIMER2_ISR                     
0     0005f590  _TestErrorRegs                  
0     000838c7  _USBA_ISR                       
0     000838d1  _USER10_ISR                     
0     000838db  _USER11_ISR                     
0     000838e5  _USER12_ISR                     
0     000838ef  _USER1_ISR                      
0     000838f9  _USER2_ISR                      
0     00083903  _USER3_ISR                      
0     0008390d  _USER4_ISR                      
0     00083917  _USER5_ISR                      
0     00083921  _USER6_ISR                      
0     0008392b  _USER7_ISR                      
0     00083935  _USER8_ISR                      
0     0008393f  _USER9_ISR                      
0     00083949  _WAKE_ISR                       
0     00007000  _WdRegs                         
0     00083953  _XINT1_ISR                      
0     0008395d  _XINT2_ISR                      
0     00083967  _XINT3_ISR                      
0     00083971  _XINT4_ISR                      
0     0008397b  _XINT5_ISR                      
0     00007920  _XbarRegs                       
0     00007070  _XintRegs                       
0     00000600  __STACK_END                     
abs   00000200  __STACK_SIZE                    
0     0000a802  ___TI_cleanup_ptr               
0     0000a804  ___TI_dtors_ptr                 
0     0000a800  ___TI_enable_exit_profile_output
abs   ffffffff  ___TI_pprof_out_hndl            
abs   ffffffff  ___TI_prof_data_size            
abs   ffffffff  ___TI_prof_data_start           
abs   ffffffff  ___binit__                      
abs   ffffffff  ___c_args__                     
0     00088000  ___cinit__                      
abs   ffffffff  ___etext__                      
abs   ffffffff  ___pinit__                      
abs   ffffffff  ___text__                       
0     00083079  __args_main                     
0     0000a806  __lock                          
0     00083996  __nop                           
0     00083992  __register_lock                 
0     0008398e  __register_unlock               
0     00000400  __stack                         
0     000839a0  __system_post_cinit             
0     0008399e  __system_pre_init               
0     0000a808  __unlock                        
0     00082fb1  _abort                          
0     00082f1e  _c_int00                        
0     00082fda  _copy_in                        
0     00082fb3  _exit                           
0     0008303f  _main                           
0     0008305c  _memcpy                         
abs   ffffffff  binit                           
0     00088000  cinit                           
0     00080000  code_start                      
abs   ffffffff  etext                           
abs   ffffffff  pinit                           


GLOBAL SYMBOLS: SORTED BY Symbol Address 

page  address   name                            
----  -------   ----                            
0     00000400  __stack                         
0     00000600  __STACK_END                     
0     00000b00  _AdcaResultRegs                 
0     00000b20  _AdcbResultRegs                 
0     00000b40  _AdccResultRegs                 
0     00000b60  _AdcdResultRegs                 
0     00000c00  _CpuTimer0Regs                  
0     00000c08  _CpuTimer1Regs                  
0     00000c10  _CpuTimer2Regs                  
0     00000ce0  _PieCtrlRegs                    
0     00000d00  _EmuBMode                       
0     00000d00  _PieVectTable                   
0     00000d01  _EmuBootPins                    
0     00001000  _DmaRegs                        
0     00001400  _Cla1Regs                       
0     00004000  _EPwm1Regs                      
0     00004100  _EPwm2Regs                      
0     00004200  _EPwm3Regs                      
0     00004300  _EPwm4Regs                      
0     00004400  _EPwm5Regs                      
0     00004500  _EPwm6Regs                      
0     00004600  _EPwm7Regs                      
0     00004700  _EPwm8Regs                      
0     00004800  _EPwm9Regs                      
0     00004900  _EPwm10Regs                     
0     00004a00  _EPwm11Regs                     
0     00004b00  _EPwm12Regs                     
0     00004c00  _EPwm13Regs                     
0     00004d00  _EPwm14Regs                     
0     00004e00  _EPwm15Regs                     
0     00004f00  _EPwm16Regs                     
0     00005100  _EQep1Regs                      
0     00005140  _EQep2Regs                      
0     00005180  _EQep3Regs                      
0     00005200  _ECap1Regs                      
0     00005240  _ECap2Regs                      
0     00005280  _ECap3Regs                      
0     000052c0  _ECap4Regs                      
0     00005300  _ECap5Regs                      
0     00005340  _ECap6Regs                      
0     00005360  _HRCap6Regs                     
0     00005380  _ECap7Regs                      
0     000053a0  _HRCap7Regs                     
0     00005c00  _DacaRegs                       
0     00005c10  _DacbRegs                       
0     00005c20  _DaccRegs                       
0     00005c80  _Cmpss1Regs                     
0     00005ca0  _Cmpss2Regs                     
0     00005cc0  _Cmpss3Regs                     
0     00005ce0  _Cmpss4Regs                     
0     00005d00  _Cmpss5Regs                     
0     00005d20  _Cmpss6Regs                     
0     00005d40  _Cmpss7Regs                     
0     00005d60  _Cmpss8Regs                     
0     00005e00  _Sdfm1Regs                      
0     00005e80  _Sdfm2Regs                      
0     00006000  _McbspaRegs                     
0     00006040  _McbspbRegs                     
0     00006100  _SpiaRegs                       
0     00006110  _SpibRegs                       
0     00006120  _SpicRegs                       
0     00006130  _SpidRegs                       
0     00006340  _BgcrcCpuRegs                   
0     00006380  _BgcrcCla1Regs                  
0     00006400  _PmbusaRegs                     
0     00006600  _FsiTxaRegs                     
0     00006680  _FsiRxaRegs                     
0     00006700  _FsiTxbRegs                     
0     00006780  _FsiRxbRegs                     
0     00006880  _FsiRxcRegs                     
0     00006980  _FsiRxdRegs                     
0     00006a80  _FsiRxeRegs                     
0     00006b80  _FsiRxfRegs                     
0     00006c80  _FsiRxgRegs                     
0     00006d80  _FsiRxhRegs                     
0     00007000  _WdRegs                         
0     00007060  _NmiIntruptRegs                 
0     00007070  _XintRegs                       
0     00007200  _SciaRegs                       
0     00007210  _ScibRegs                       
0     00007220  _ScicRegs                       
0     00007230  _ScidRegs                       
0     00007300  _I2caRegs                       
0     00007340  _I2cbRegs                       
0     00007400  _AdcaRegs                       
0     00007480  _AdcbRegs                       
0     00007500  _AdccRegs                       
0     00007580  _AdcdRegs                       
0     00007900  _InputXbarRegs                  
0     00007920  _XbarRegs                       
0     00007940  _SyncSocRegs                    
0     00007980  _DmaClaSrcSelRegs               
0     00007a00  _EPwmXbarRegs                   
0     00007a80  _OutputXbarRegs                 
0     00007c00  _GpioCtrlRegs                   
0     00007f00  _GpioDataRegs                   
0     00008000  _EPWM1_ISR                      
0     00008000  _RamfuncsRunStart               
0     00008010  _RamfuncsRunEnd                 
0     0000a800  ___TI_enable_exit_profile_output
0     0000a802  ___TI_cleanup_ptr               
0     0000a804  ___TI_dtors_ptr                 
0     0000a806  __lock                          
0     0000a808  __unlock                        
0     00047000  _Emif1Regs                      
0     00047800  _Emif2Regs                      
0     00048000  _CanaRegs                       
0     0004a000  _CanbRegs                       
0     00057e00  _EcatssRegs                     
0     00057f00  _EcatssConfigRegs               
0     0005c400  _McanssRegs                     
0     0005c600  _McanRegs                       
0     0005c800  _McanErrorRegs                  
0     0005ce00  _Cpu1toCpu2IpcRegs              
0     0005ce40  _Cpu1toCmIpcRegs                
0     0005d000  _DevCfgRegs                     
0     0005d200  _ClkCfgRegs                     
0     0005d300  _CpuSysRegs                     
0     0005d400  _SysStatusRegs                  
0     0005d500  _SysPeriphAcRegs                
0     0005d700  _AnalogSubsysRegs               
0     0005dc00  _CmConfRegs                     
0     0005e000  _HwbistRegs                     
0     0005e700  _Dcc0Regs                       
0     0005e740  _Dcc1Regs                       
0     0005e780  _Dcc2Regs                       
0     0005e800  _EradGlobalRegs                 
0     0005e900  _EradHwbpRegs                   
0     0005e980  _EradCounterRegs                
0     0005ea00  _EradCrcRegs                    
0     0005f000  _DcsmZ1Regs                     
0     0005f080  _DcsmZ2Regs                     
0     0005f0c0  _DcsmCommonRegs                 
0     0005f400  _MemCfgRegs                     
0     0005f4c0  _Emif1ConfigRegs                
0     0005f4e0  _Emif2ConfigRegs                
0     0005f500  _AccessProtectionRegs           
0     0005f540  _MemoryErrorRegs                
0     0005f580  _RomWaitStateRegs               
0     0005f588  _RomPrefetchRegs                
0     0005f590  _TestErrorRegs                  
0     0005f800  _Flash0CtrlRegs                 
0     0005fb00  _Flash0EccRegs                  
0     00078000  _DcsmZ1Otp                      
0     00078200  _DcsmZ2Otp                      
0     00080000  code_start                      
0     00082000  _InitXbar                       
0     00082841  _InitGpio                       
0     00082bfa  _InitEPwm                       
0     00082d11  _InitSysCtrl                    
0     00082e08  _AdcSetMode                     
0     00082ebf  _InitAdca                       
0     00082f1e  _c_int00                        
0     00082f74  _CalAdcINL                      
0     00082fb1  C$$EXIT                         
0     00082fb1  _abort                          
0     00082fb3  _exit                           
0     00082fda  _copy_in                        
0     00082ffe  _InitPieVectTable               
0     00083020  _InitPieCtrl                    
0     0008303f  _main                           
0     0008305c  _memcpy                         
0     00083079  __args_main                     
0     0008308b  _CLA1CRC_INT_ISR                
0     00083098  _CLB1_ISR                       
0     000830a5  _CLB2_ISR                       
0     000830b2  _CLB3_ISR                       
0     000830bf  _CLB4_ISR                       
0     000830cc  _CLB5_ISR                       
0     000830d9  _CLB6_ISR                       
0     000830e6  _CLB7_ISR                       
0     000830f3  _CLB8_ISR                       
0     00083100  _CMTOCPUXIPC0_ISR               
0     0008310d  _CMTOCPUXIPC1_ISR               
0     0008311a  _CMTOCPUXIPC2_ISR               
0     00083127  _CMTOCPUXIPC3_ISR               
0     00083134  _CMTOCPUXIPC4_ISR               
0     00083141  _CMTOCPUXIPC5_ISR               
0     0008314e  _CMTOCPUXIPC6_ISR               
0     0008315b  _CMTOCPUXIPC7_ISR               
0     00083168  _CM_STATUS_ISR                  
0     00083175  _CPUCRC_INT_ISR                 
0     00083182  _ECATRSTINTN_ISR                
0     0008318f  _ECATSYNC0_ISR                  
0     0008319c  _ECATSYNC1_ISR                  
0     000831a9  _ECAT_ISR                       
0     000831b6  _EMPTY_ISR                      
0     000831c3  _EPWM13_ISR                     
0     000831d0  _EPWM13_TZ_ISR                  
0     000831dd  _EPWM14_ISR                     
0     000831ea  _EPWM14_TZ_ISR                  
0     000831f7  _EPWM15_ISR                     
0     00083204  _EPWM15_TZ_ISR                  
0     00083211  _EPWM16_ISR                     
0     0008321e  _EPWM16_TZ_ISR                  
0     0008322b  _FMC_ISR                        
0     00083238  _FSIRXA1_ISR                    
0     00083245  _FSIRXA2_ISR                    
0     00083252  _FSIRXB1_ISR                    
0     0008325f  _FSIRXB2_ISR                    
0     0008326c  _FSIRXC1_ISR                    
0     00083279  _FSIRXC2_ISR                    
0     00083286  _FSIRXD1_ISR                    
0     00083293  _FSIRXD2_ISR                    
0     000832a0  _FSIRXE1_ISR                    
0     000832ad  _FSIRXE2_ISR                    
0     000832ba  _FSIRXF1_ISR                    
0     000832c7  _FSIRXF2_ISR                    
0     000832d4  _FSIRXG1_ISR                    
0     000832e1  _FSIRXG2_ISR                    
0     000832ee  _FSIRXH1_ISR                    
0     000832fb  _FSIRXH2_ISR                    
0     00083308  _FSITXA1_ISR                    
0     00083315  _FSITXA2_ISR                    
0     00083322  _FSITXB1_ISR                    
0     0008332f  _FSITXB2_ISR                    
0     0008333c  _I2CA_HIGH_ISR                  
0     00083349  _MCANSS0_ISR                    
0     00083356  _MCANSS1_ISR                    
0     00083363  _MCANSS_ECC_CORR_PLS_ISR        
0     00083370  _MCANSS_WAKE_AND_TS_PLS_ISR     
0     0008337d  _PBIST_ISR                      
0     0008338a  _PMBUSA_ISR                     
0     00083397  _PwmViennaOn                    
0     000833a4  _SDFM1DR1_ISR                   
0     000833b1  _SDFM1DR2_ISR                   
0     000833be  _SDFM1DR3_ISR                   
0     000833cb  _SDFM1DR4_ISR                   
0     000833d8  _SDFM2DR1_ISR                   
0     000833e5  _SDFM2DR2_ISR                   
0     000833f2  _SDFM2DR3_ISR                   
0     000833ff  _SDFM2DR4_ISR                   
0     0008340c  _SPID_RX_ISR                    
0     00083419  _SPID_TX_ISR                    
0     00083426  _SYS_ERR_ISR                    
0     00083433  _InitWatchdog                   
0     0008343f  _ADCA1_ISR                      
0     00083449  _ADCA2_ISR                      
0     00083453  _ADCA3_ISR                      
0     0008345d  _ADCA4_ISR                      
0     00083467  _ADCA_EVT_ISR                   
0     00083471  _ADCB1_ISR                      
0     0008347b  _ADCB2_ISR                      
0     00083485  _ADCB3_ISR                      
0     0008348f  _ADCB4_ISR                      
0     00083499  _ADCB_EVT_ISR                   
0     000834a3  _ADCC1_ISR                      
0     000834ad  _ADCC2_ISR                      
0     000834b7  _ADCC3_ISR                      
0     000834c1  _ADCC4_ISR                      
0     000834cb  _ADCC_EVT_ISR                   
0     000834d5  _ADCD1_ISR                      
0     000834df  _ADCD2_ISR                      
0     000834e9  _ADCD3_ISR                      
0     000834f3  _ADCD4_ISR                      
0     000834fd  _ADCD_EVT_ISR                   
0     00083507  _CANA0_ISR                      
0     00083511  _CANA1_ISR                      
0     0008351b  _CANB0_ISR                      
0     00083525  _CANB1_ISR                      
0     0008352f  _CIPC0_ISR                      
0     00083539  _CIPC1_ISR                      
0     00083543  _CIPC2_ISR                      
0     0008354d  _CIPC3_ISR                      
0     00083557  _CLA1_1_ISR                     
0     00083561  _CLA1_2_ISR                     
0     0008356b  _CLA1_3_ISR                     
0     00083575  _CLA1_4_ISR                     
0     0008357f  _CLA1_5_ISR                     
0     00083589  _CLA1_6_ISR                     
0     00083593  _CLA1_7_ISR                     
0     0008359d  _CLA1_8_ISR                     
0     000835a7  _CLA_OVERFLOW_ISR               
0     000835b1  _CLA_UNDERFLOW_ISR              
0     000835bb  _DATALOG_ISR                    
0     000835c5  _DMA_CH1_ISR                    
0     000835cf  _DMA_CH2_ISR                    
0     000835d9  _DMA_CH3_ISR                    
0     000835e3  _DMA_CH4_ISR                    
0     000835ed  _DMA_CH5_ISR                    
0     000835f7  _DMA_CH6_ISR                    
0     00083601  _ECAP1_ISR                      
0     0008360b  _ECAP2_ISR                      
0     00083615  _ECAP3_ISR                      
0     0008361f  _ECAP4_ISR                      
0     00083629  _ECAP5_ISR                      
0     00083633  _ECAP6_2_ISR                    
0     0008363d  _ECAP6_ISR                      
0     00083647  _ECAP7_2_ISR                    
0     00083651  _ECAP7_ISR                      
0     0008365b  _EMIF_ERROR_ISR                 
0     00083665  _EMU_ISR                        
0     0008366f  _EPWM10_ISR                     
0     00083679  _EPWM10_TZ_ISR                  
0     00083683  _EPWM11_ISR                     
0     0008368d  _EPWM11_TZ_ISR                  
0     00083697  _EPWM12_ISR                     
0     000836a1  _EPWM12_TZ_ISR                  
0     000836ab  _EPWM1_TZ_ISR                   
0     000836b5  _EPWM2_ISR                      
0     000836bf  _EPWM2_TZ_ISR                   
0     000836c9  _EPWM3_ISR                      
0     000836d3  _EPWM3_TZ_ISR                   
0     000836dd  _EPWM4_ISR                      
0     000836e7  _EPWM4_TZ_ISR                   
0     000836f1  _EPWM5_ISR                      
0     000836fb  _EPWM5_TZ_ISR                   
0     00083705  _EPWM6_ISR                      
0     0008370f  _EPWM6_TZ_ISR                   
0     00083719  _EPWM7_ISR                      
0     00083723  _EPWM7_TZ_ISR                   
0     0008372d  _EPWM8_ISR                      
0     00083737  _EPWM8_TZ_ISR                   
0     00083741  _EPWM9_ISR                      
0     0008374b  _EPWM9_TZ_ISR                   
0     00083755  _EQEP1_ISR                      
0     0008375f  _EQEP2_ISR                      
0     00083769  _EQEP3_ISR                      
0     00083773  _FPU_OFLOW_ISR                  
0     0008377d  _FPU_UFLOW_ISR                  
0     00083787  _I2CA_FIFO_ISR                  
0     00083791  _I2CA_ISR                       
0     0008379b  _I2CB_FIFO_ISR                  
0     000837a5  _I2CB_ISR                       
0     000837af  _ILLEGAL_ISR                    
0     000837b9  _MCBSPA_RX_ISR                  
0     000837c3  _MCBSPA_TX_ISR                  
0     000837cd  _MCBSPB_RX_ISR                  
0     000837d7  _MCBSPB_TX_ISR                  
0     000837e1  _NMI_ISR                        
0     000837eb  _NOTUSED_ISR                    
0     000837f5  _PIE_RESERVED_ISR               
0     000837ff  _RTOS_ISR                       
0     00083809  _SCIA_RX_ISR                    
0     00083813  _SCIA_TX_ISR                    
0     0008381d  _SCIB_RX_ISR                    
0     00083827  _SCIB_TX_ISR                    
0     00083831  _SCIC_RX_ISR                    
0     0008383b  _SCIC_TX_ISR                    
0     00083845  _SCID_RX_ISR                    
0     0008384f  _SCID_TX_ISR                    
0     00083859  _SDFM1_ISR                      
0     00083863  _SDFM2_ISR                      
0     0008386d  _SPIA_RX_ISR                    
0     00083877  _SPIA_TX_ISR                    
0     00083881  _SPIB_RX_ISR                    
0     0008388b  _SPIB_TX_ISR                    
0     00083895  _SPIC_RX_ISR                    
0     0008389f  _SPIC_TX_ISR                    
0     000838a9  _TIMER0_ISR                     
0     000838b3  _TIMER1_ISR                     
0     000838bd  _TIMER2_ISR                     
0     000838c7  _USBA_ISR                       
0     000838d1  _USER10_ISR                     
0     000838db  _USER11_ISR                     
0     000838e5  _USER12_ISR                     
0     000838ef  _USER1_ISR                      
0     000838f9  _USER2_ISR                      
0     00083903  _USER3_ISR                      
0     0008390d  _USER4_ISR                      
0     00083917  _USER5_ISR                      
0     00083921  _USER6_ISR                      
0     0008392b  _USER7_ISR                      
0     00083935  _USER8_ISR                      
0     0008393f  _USER9_ISR                      
0     00083949  _WAKE_ISR                       
0     00083953  _XINT1_ISR                      
0     0008395d  _XINT2_ISR                      
0     00083967  _XINT3_ISR                      
0     00083971  _XINT4_ISR                      
0     0008397b  _XINT5_ISR                      
0     00083985  _EnableInterrupts               
0     0008398e  __register_unlock               
0     00083992  __register_lock                 
0     00083996  __nop                           
0     00083997  _SetInterrupts                  
0     0008399e  __system_pre_init               
0     000839a0  __system_post_cinit             
0     00086000  _RamfuncsLoadStart              
0     00086010  _RamfuncsLoadEnd                
0     00088000  ___cinit__                      
0     00088000  cinit                           
0     0008801c  _PieVectTableInit               
abs   00000010  _RamfuncsLoadSize               
abs   00000010  _RamfuncsRunSize                
abs   00000200  __STACK_SIZE                    
abs   ffffffff  .text                           
abs   ffffffff  ___TI_pprof_out_hndl            
abs   ffffffff  ___TI_prof_data_size            
abs   ffffffff  ___TI_prof_data_start           
abs   ffffffff  ___binit__                      
abs   ffffffff  ___c_args__                     
abs   ffffffff  ___etext__                      
abs   ffffffff  ___pinit__                      
abs   ffffffff  ___text__                       
abs   ffffffff  binit                           
abs   ffffffff  etext                           
abs   ffffffff  pinit                           

[398 symbols]

5/ Program running from FLASH / Linker: "2838x_flash_lnk_cpu1.cmd" from C2000Ware library

ISR coded in asm. ISR in .sect ".text". Extract of .cmd file regarding the section ".text": .text     :>> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(4)

Latency between trigger of PWM1 and rising edge (begin of jitter) of 1µs pulse : ~137ns, jitter in the rising edge ~5ns (~1 clock pulse)

Here is the .map file:

******************************************************************************
             TMS320C2000 Linker PC v21.6.0                     
******************************************************************************
>> Linked Wed Feb 23 09:06:08 2022

OUTPUT FILE NAME:   <psu1kWvienna_F2838x.out>
ENTRY POINT SYMBOL: "_c_int00"  address: 00082f1e


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  BOOT_RSVD             00000002   000001ae  00000000  000001ae  RWIX
  RAMM0                 000001b0   00000250  00000000  00000250  RWIX
  RAMM1                 00000400   00000400  00000200  00000200  RWIX
  ADCA_RESULT           00000b00   00000020  00000018  00000008  RWIX
  ADCB_RESULT           00000b20   00000020  00000018  00000008  RWIX
  ADCC_RESULT           00000b40   00000020  00000018  00000008  RWIX
  ADCD_RESULT           00000b60   00000020  00000018  00000008  RWIX
  CPU_TIMER0            00000c00   00000008  00000008  00000000  RWIX
  CPU_TIMER1            00000c08   00000008  00000008  00000000  RWIX
  CPU_TIMER2            00000c10   00000008  00000008  00000000  RWIX
  PIE_CTRL              00000ce0   00000020  0000001a  00000006  RWIX
  PIE_VECT_TABLE        00000d00   00000200  000001c0  00000040  RWIX
  DMA                   00001000   000000e0  000000e0  00000000  RWIX
  CLA1                  00001400   00000048  00000048  00000000  RWIX
  EPWM1                 00004000   00000100  00000100  00000000  RWIX
  EPWM2                 00004100   00000100  00000100  00000000  RWIX
  EPWM3                 00004200   00000100  00000100  00000000  RWIX
  EPWM4                 00004300   00000100  00000100  00000000  RWIX
  EPWM5                 00004400   00000100  00000100  00000000  RWIX
  EPWM6                 00004500   00000100  00000100  00000000  RWIX
  EPWM7                 00004600   00000100  00000100  00000000  RWIX
  EPWM8                 00004700   00000100  00000100  00000000  RWIX
  EPWM9                 00004800   00000100  00000100  00000000  RWIX
  EPWM10                00004900   00000100  00000100  00000000  RWIX
  EPWM11                00004a00   00000100  00000100  00000000  RWIX
  EPWM12                00004b00   00000100  00000100  00000000  RWIX
  EPWM13                00004c00   00000100  00000100  00000000  RWIX
  EPWM14                00004d00   00000100  00000100  00000000  RWIX
  EPWM15                00004e00   00000100  00000100  00000000  RWIX
  EPWM16                00004f00   00000100  00000100  00000000  RWIX
  EQEP1                 00005100   00000040  00000038  00000008  RWIX
  EQEP2                 00005140   00000040  00000038  00000008  RWIX
  EQEP3                 00005180   00000040  00000038  00000008  RWIX
  ECAP1                 00005200   00000020  00000020  00000000  RWIX
  ECAP2                 00005240   00000020  00000020  00000000  RWIX
  ECAP3                 00005280   00000020  00000020  00000000  RWIX
  ECAP4                 000052c0   00000020  00000020  00000000  RWIX
  ECAP5                 00005300   00000020  00000020  00000000  RWIX
  ECAP6                 00005340   00000020  00000020  00000000  RWIX
  HRCAP6                00005360   00000020  00000016  0000000a  RWIX
  ECAP7                 00005380   00000020  00000020  00000000  RWIX
  HRCAP7                000053a0   00000020  00000016  0000000a  RWIX
  DACA                  00005c00   00000010  00000007  00000009  RWIX
  DACB                  00005c10   00000010  00000007  00000009  RWIX
  DACC                  00005c20   00000010  00000007  00000009  RWIX
  CMPSS1                00005c80   00000020  0000001b  00000005  RWIX
  CMPSS2                00005ca0   00000020  0000001b  00000005  RWIX
  CMPSS3                00005cc0   00000020  0000001b  00000005  RWIX
  CMPSS4                00005ce0   00000020  0000001b  00000005  RWIX
  CMPSS5                00005d00   00000020  0000001b  00000005  RWIX
  CMPSS6                00005d20   00000020  0000001b  00000005  RWIX
  CMPSS7                00005d40   00000020  0000001b  00000005  RWIX
  CMPSS8                00005d60   00000020  0000001b  00000005  RWIX
  SDFM1                 00005e00   00000080  00000080  00000000  RWIX
  SDFM2                 00005e80   00000080  00000080  00000000  RWIX
  MCBSPA                00006000   00000040  00000024  0000001c  RWIX
  MCBSPB                00006040   00000040  00000024  0000001c  RWIX
  SPIA                  00006100   00000010  00000010  00000000  RWIX
  SPIB                  00006110   00000010  00000010  00000000  RWIX
  SPIC                  00006120   00000010  00000010  00000000  RWIX
  SPID                  00006130   00000010  00000010  00000000  RWIX
  BGCRC                 00006340   00000080  00000080  00000000  RWIX
  PMBUSA                00006400   00000020  0000001e  00000002  RWIX
  FSITXA                00006600   00000080  00000042  0000003e  RWIX
  FSIRXA                00006680   00000080  00000042  0000003e  RWIX
  FSI_TXB               00006700   00000080  00000042  0000003e  RWIX
  FSI_RXB               00006780   00000080  00000042  0000003e  RWIX
  FSI_RXC               00006880   00000080  00000042  0000003e  RWIX
  FSI_RXD               00006980   00000080  00000042  0000003e  RWIX
  FSI_RXE               00006a80   00000080  00000042  0000003e  RWIX
  FSI_RXF               00006b80   00000080  00000042  0000003e  RWIX
  FSI_RXG               00006c80   00000080  00000042  0000003e  RWIX
  FSI_RXH               00006d80   00000080  00000042  0000003e  RWIX
  WD                    00007000   00000040  0000002b  00000015  RWIX
  NMIINTRUPT            00007060   00000010  0000000c  00000004  RWIX
  XINT                  00007070   00000010  0000000b  00000005  RWIX
  SCIA                  00007200   00000010  00000010  00000000  RWIX
  SCIB                  00007210   00000010  00000010  00000000  RWIX
  SCIC                  00007220   00000010  00000010  00000000  RWIX
  SCID                  00007230   00000010  00000010  00000000  RWIX
  I2CA                  00007300   00000040  00000022  0000001e  RWIX
  I2CB                  00007340   00000040  00000022  0000001e  RWIX
  ADCA                  00007400   00000080  0000007c  00000004  RWIX
  ADCB                  00007480   00000080  0000007c  00000004  RWIX
  ADCC                  00007500   00000080  0000007c  00000004  RWIX
  ADCD                  00007580   00000080  0000007c  00000004  RWIX
  INPUT_XBAR            00007900   00000020  00000020  00000000  RWIX
  XBAR                  00007920   00000020  00000010  00000010  RWIX
  SYNC_SOC              00007940   00000010  00000006  0000000a  RWIX
  DMA_CLA_SRC_SEL       00007980   00000040  0000001a  00000026  RWIX
  EPWM_XBAR             00007a00   00000040  00000040  00000000  RWIX
  OUTPUT_XBAR           00007a80   00000040  00000040  00000000  RWIX
  GPIOCTRL              00007c00   00000180  00000180  00000000  RWIX
  GPIODATA              00007f00   00000030  00000030  00000000  RWIX
  RAMLS0                00008000   00000800  00000000  00000800  RWIX
  RAMLS1                00008800   00000800  00000000  00000800  RWIX
  RAMLS2                00009000   00000800  00000000  00000800  RWIX
  RAMLS3                00009800   00000800  00000000  00000800  RWIX
  RAMLS4                0000a000   00000800  00000000  00000800  RWIX
  RAMLS5                0000a800   00000800  0000000a  000007f6  RWIX
  RAMLS6                0000b000   00000800  00000000  00000800  RWIX
  RAMLS7                0000b800   00000800  00000000  00000800  RWIX
  RAMD0                 0000c000   00000800  00000000  00000800  RWIX
  RAMD1                 0000c800   00000800  00000000  00000800  RWIX
  RAMGS0                0000d000   00001000  00000000  00001000  RWIX
  RAMGS1                0000e000   00001000  00000000  00001000  RWIX
  RAMGS2                0000f000   00001000  00000000  00001000  RWIX
  RAMGS3                00010000   00001000  00000000  00001000  RWIX
  RAMGS4                00011000   00001000  00000000  00001000  RWIX
  RAMGS5                00012000   00001000  00000000  00001000  RWIX
  RAMGS6                00013000   00001000  00000000  00001000  RWIX
  RAMGS7                00014000   00001000  00000000  00001000  RWIX
  RAMGS8                00015000   00001000  00000000  00001000  RWIX
  RAMGS9                00016000   00001000  00000000  00001000  RWIX
  RAMGS10               00017000   00001000  00000000  00001000  RWIX
  RAMGS11               00018000   00001000  00000000  00001000  RWIX
  RAMGS12               00019000   00001000  00000000  00001000  RWIX
  RAMGS13               0001a000   00001000  00000000  00001000  RWIX
  RAMGS14               0001b000   00001000  00000000  00001000  RWIX
  RAMGS15               0001c000   00001000  00000000  00001000  RWIX
  CMTOCPURAM            00038000   00000800  00000000  00000800  RWIX
  CPUTOCMRAM            00039000   00000800  00000000  00000800  RWIX
  CPU1TOCPU2RAM         0003a000   00000800  00000000  00000800  RWIX
  CPU2TOCPU1RAM         0003b000   00000800  00000000  00000800  RWIX
  EMIF1                 00047000   00000800  00000028  000007d8  RWIX
  EMIF2                 00047800   00000800  00000028  000007d8  RWIX
  CANA                  00048000   00000800  00000162  0000069e  RWIX
  CANA_MSG_RAM          00049000   00000800  00000000  00000800  RWIX
  CANB                  0004a000   00000800  00000162  0000069e  RWIX
  CANB_MSG_RAM          0004b000   00000800  00000000  00000800  RWIX
  ECATSS                00057e00   00000100  00000024  000000dc  RWIX
  ECATSS_CONFIG         00057f00   00000100  00000016  000000ea  RWIX
  MCANSS                0005c400   00000040  00000016  0000002a  RWIX
  MCAN                  0005c600   00000200  0000007e  00000182  RWIX
  MCAN_ERROR            0005c800   00000400  00000108  000002f8  RWIX
  CPU1TOCPU2_IPC_CPU1VI 0005ce00   00000040  00000026  0000001a  RWIX
  CPU1TOCM_IPC_CPU1VIEW 0005ce40   00000040  00000024  0000001c  RWIX
  DEV_CFG               0005d000   000001a0  000001a0  00000000  RWIX
  CLK_CFG               0005d200   00000100  0000003a  000000c6  RWIX
  CPU_SYS               0005d300   00000100  000000a0  00000060  RWIX
  SYS_STATUS            0005d400   00000100  00000018  000000e8  RWIX
  PERIPH_AC             0005d500   00000200  00000200  00000000  RWIX
  ANALOG_SUBSYS         0005d700   00000100  000000e2  0000001e  RWIX
  CM_CONF               0005dc00   00000400  00000400  00000000  RWIX
  HWBIST                0005e000   000000d0  0000008e  00000042  RWIX
  DCC0                  0005e700   00000040  0000002c  00000014  RWIX
  DCC1                  0005e740   00000040  0000002c  00000014  RWIX
  DCC2                  0005e780   00000040  0000002c  00000014  RWIX
  ERAD_GLOBAL_REGISTERS 0005e800   00000100  00000014  000000ec  RWIX
  ERAD_HWBP_REGISTERS   0005e900   00000080  00000008  00000078  RWIX
  ERAD_COUNTER_REGISTER 0005e980   00000080  0000000c  00000074  RWIX
  ERAD_CRC_REGISTERS    0005ea00   00000100  00000006  000000fa  RWIX
  DCSM_Z1               0005f000   00000040  0000003e  00000002  RWIX
  DCSM_Z2               0005f080   00000040  0000002c  00000014  RWIX
  DCSM_COMMON           0005f0c0   00000040  0000001e  00000022  RWIX
  MEMCFG                0005f400   000000c0  000000ae  00000012  RWIX
  EMIF1CONFIG           0005f4c0   00000020  0000000a  00000016  RWIX
  EMIF2CONFIG           0005f4e0   00000020  0000000a  00000016  RWIX
  ACCESSPROTECTION      0005f500   00000040  0000002e  00000012  RWIX
  MEMORYERROR           0005f540   00000040  0000003a  00000006  RWIX
  ROMWAITSTATE          0005f580   00000008  00000002  00000006  RWIX
  ROMPREFETCH           0005f588   00000008  00000002  00000006  RWIX
  TEST_ERROR            0005f590   0000000f  00000006  00000009  RWIX
  FLASH0_CTRL           0005f800   00000300  00000182  0000017e  RWIX
  FLASH0_ECC            0005fb00   00000040  00000028  00000018  RWIX
  DCSM_Z1_OTP           00078000   00000020  00000020  00000000  RWIX
  DCSM_Z2_OTP           00078200   00000020  00000014  0000000c  RWIX
  BEGIN                 00080000   00000002  00000002  00000000  RWIX
  FLASH0                00080002   00001ffe  00000000  00001ffe  RWIX
  FLASH1                00082000   00002000  000019b1  0000064f  RWIX
  FLASH2                00084000   00002000  00000000  00002000  RWIX
  FLASH3                00086000   00002000  00000000  00002000  RWIX
  FLASH4                00088000   00008000  000001da  00007e26  RWIX
  FLASH5                00090000   00008000  00000000  00008000  RWIX
  FLASH6                00098000   00008000  00000000  00008000  RWIX
  FLASH7                000a0000   00008000  00000000  00008000  RWIX
  FLASH8                000a8000   00008000  00000000  00008000  RWIX
  FLASH9                000b0000   00008000  00000000  00008000  RWIX
  FLASH10               000b8000   00002000  00000000  00002000  RWIX
  FLASH11               000ba000   00002000  00000000  00002000  RWIX
  FLASH12               000bc000   00002000  00000000  00002000  RWIX
  FLASH13               000be000   00002000  00000000  00002000  RWIX
  RESET                 003fffc0   00000002  00000000  00000002  RWIX


SECTION ALLOCATION MAP

 output                                  attributes/
section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------
codestart 
*          0    00080000    00000002     
                  00080000    00000002     F2838x_CodeStartBranch.obj (codestart)

.cinit     0    00088000    0000001a     
                  00088000    0000000e     rts2800_fpu32.lib : exit.c.obj (.cinit)
                  0008800e    00000005                       : _lock.c.obj (.cinit:__lock)
                  00088013    00000005                       : _lock.c.obj (.cinit:__unlock)
                  00088018    00000002     --HOLE-- [fill = 0]

.reset     0    003fffc0    00000002     DSECT
                  003fffc0    00000002     rts2800_fpu32.lib : boot28.asm.obj (.reset)

.stack     0    00000400    00000200     UNINITIALIZED
                  00000400    00000200     --HOLE--

.pinit     0    00082000    00000000     UNINITIALIZED

.ebss      0    0000a800    0000000a     UNINITIALIZED
                  0000a800    00000006     rts2800_fpu32.lib : exit.c.obj (.ebss)
                  0000a806    00000002                       : _lock.c.obj (.ebss:__lock)
                  0000a808    00000002                       : _lock.c.obj (.ebss:__unlock)

AdcaResultFile 
*          0    00000b00    00000018     UNINITIALIZED
                  00000b00    00000018     f2838x_GlobalVariableDefs.obj (AdcaResultFile)

AdcbResultFile 
*          0    00000b20    00000018     UNINITIALIZED
                  00000b20    00000018     f2838x_GlobalVariableDefs.obj (AdcbResultFile)

AdccResultFile 
*          0    00000b40    00000018     UNINITIALIZED
                  00000b40    00000018     f2838x_GlobalVariableDefs.obj (AdccResultFile)

AdcdResultFile 
*          0    00000b60    00000018     UNINITIALIZED
                  00000b60    00000018     f2838x_GlobalVariableDefs.obj (AdcdResultFile)

CpuTimer0RegsFile 
*          0    00000c00    00000008     UNINITIALIZED
                  00000c00    00000008     f2838x_GlobalVariableDefs.obj (CpuTimer0RegsFile)

CpuTimer1RegsFile 
*          0    00000c08    00000008     UNINITIALIZED
                  00000c08    00000008     f2838x_GlobalVariableDefs.obj (CpuTimer1RegsFile)

CpuTimer2RegsFile 
*          0    00000c10    00000008     UNINITIALIZED
                  00000c10    00000008     f2838x_GlobalVariableDefs.obj (CpuTimer2RegsFile)

PieCtrlRegsFile 
*          0    00000ce0    0000001a     UNINITIALIZED
                  00000ce0    0000001a     f2838x_GlobalVariableDefs.obj (PieCtrlRegsFile)

PieVectTableFile 
*          0    00000d00    000001c0     UNINITIALIZED
                  00000d00    000001c0     f2838x_GlobalVariableDefs.obj (PieVectTableFile)

EmuKeyVar 
*          0    00000d00    00000000     UNINITIALIZED

EmuBModeVar 
*          0    00000d00    00000001     UNINITIALIZED
                  00000d00    00000001     f2838x_GlobalVariableDefs.obj (EmuBModeVar)

EmuBootPinsVar 
*          0    00000d01    00000001     UNINITIALIZED
                  00000d01    00000001     f2838x_GlobalVariableDefs.obj (EmuBootPinsVar)

FlashCallbackVar 
*          0    00000d02    00000000     UNINITIALIZED

FlashScalingVar 
*          0    00000d02    00000000     UNINITIALIZED

DmaRegsFile 
*          0    00001000    000000e0     UNINITIALIZED
                  00001000    000000e0     f2838x_GlobalVariableDefs.obj (DmaRegsFile)

Cla1RegsFile 
*          0    00001400    00000048     UNINITIALIZED
                  00001400    00000048     f2838x_GlobalVariableDefs.obj (Cla1RegsFile)

EPwm1RegsFile 
*          0    00004000    00000100     UNINITIALIZED
                  00004000    00000100     f2838x_GlobalVariableDefs.obj (EPwm1RegsFile)

EPwm2RegsFile 
*          0    00004100    00000100     UNINITIALIZED
                  00004100    00000100     f2838x_GlobalVariableDefs.obj (EPwm2RegsFile)

EPwm3RegsFile 
*          0    00004200    00000100     UNINITIALIZED
                  00004200    00000100     f2838x_GlobalVariableDefs.obj (EPwm3RegsFile)

EPwm4RegsFile 
*          0    00004300    00000100     UNINITIALIZED
                  00004300    00000100     f2838x_GlobalVariableDefs.obj (EPwm4RegsFile)

EPwm5RegsFile 
*          0    00004400    00000100     UNINITIALIZED
                  00004400    00000100     f2838x_GlobalVariableDefs.obj (EPwm5RegsFile)

EPwm6RegsFile 
*          0    00004500    00000100     UNINITIALIZED
                  00004500    00000100     f2838x_GlobalVariableDefs.obj (EPwm6RegsFile)

EPwm7RegsFile 
*          0    00004600    00000100     UNINITIALIZED
                  00004600    00000100     f2838x_GlobalVariableDefs.obj (EPwm7RegsFile)

EPwm8RegsFile 
*          0    00004700    00000100     UNINITIALIZED
                  00004700    00000100     f2838x_GlobalVariableDefs.obj (EPwm8RegsFile)

EPwm9RegsFile 
*          0    00004800    00000100     UNINITIALIZED
                  00004800    00000100     f2838x_GlobalVariableDefs.obj (EPwm9RegsFile)

EPwm10RegsFile 
*          0    00004900    00000100     UNINITIALIZED
                  00004900    00000100     f2838x_GlobalVariableDefs.obj (EPwm10RegsFile)

EPwm11RegsFile 
*          0    00004a00    00000100     UNINITIALIZED
                  00004a00    00000100     f2838x_GlobalVariableDefs.obj (EPwm11RegsFile)

EPwm12RegsFile 
*          0    00004b00    00000100     UNINITIALIZED
                  00004b00    00000100     f2838x_GlobalVariableDefs.obj (EPwm12RegsFile)

EPwm13RegsFile 
*          0    00004c00    00000100     UNINITIALIZED
                  00004c00    00000100     f2838x_GlobalVariableDefs.obj (EPwm13RegsFile)

EPwm14RegsFile 
*          0    00004d00    00000100     UNINITIALIZED
                  00004d00    00000100     f2838x_GlobalVariableDefs.obj (EPwm14RegsFile)

EPwm15RegsFile 
*          0    00004e00    00000100     UNINITIALIZED
                  00004e00    00000100     f2838x_GlobalVariableDefs.obj (EPwm15RegsFile)

EPwm16RegsFile 
*          0    00004f00    00000100     UNINITIALIZED
                  00004f00    00000100     f2838x_GlobalVariableDefs.obj (EPwm16RegsFile)

EQep1RegsFile 
*          0    00005100    00000038     UNINITIALIZED
                  00005100    00000038     f2838x_GlobalVariableDefs.obj (EQep1RegsFile)

EQep2RegsFile 
*          0    00005140    00000038     UNINITIALIZED
                  00005140    00000038     f2838x_GlobalVariableDefs.obj (EQep2RegsFile)

EQep3RegsFile 
*          0    00005180    00000038     UNINITIALIZED
                  00005180    00000038     f2838x_GlobalVariableDefs.obj (EQep3RegsFile)

ECap1RegsFile 
*          0    00005200    00000020     UNINITIALIZED
                  00005200    00000020     f2838x_GlobalVariableDefs.obj (ECap1RegsFile)

ECap2RegsFile 
*          0    00005240    00000020     UNINITIALIZED
                  00005240    00000020     f2838x_GlobalVariableDefs.obj (ECap2RegsFile)

ECap3RegsFile 
*          0    00005280    00000020     UNINITIALIZED
                  00005280    00000020     f2838x_GlobalVariableDefs.obj (ECap3RegsFile)

ECap4RegsFile 
*          0    000052c0    00000020     UNINITIALIZED
                  000052c0    00000020     f2838x_GlobalVariableDefs.obj (ECap4RegsFile)

ECap5RegsFile 
*          0    00005300    00000020     UNINITIALIZED
                  00005300    00000020     f2838x_GlobalVariableDefs.obj (ECap5RegsFile)

ECap6RegsFile 
*          0    00005340    00000020     UNINITIALIZED
                  00005340    00000020     f2838x_GlobalVariableDefs.obj (ECap6RegsFile)

HRCap6RegsFile 
*          0    00005360    00000016     UNINITIALIZED
                  00005360    00000016     f2838x_GlobalVariableDefs.obj (HRCap6RegsFile)

ECap7RegsFile 
*          0    00005380    00000020     UNINITIALIZED
                  00005380    00000020     f2838x_GlobalVariableDefs.obj (ECap7RegsFile)

HRCap7RegsFile 
*          0    000053a0    00000016     UNINITIALIZED
                  000053a0    00000016     f2838x_GlobalVariableDefs.obj (HRCap7RegsFile)

DacaRegsFile 
*          0    00005c00    00000007     UNINITIALIZED
                  00005c00    00000007     f2838x_GlobalVariableDefs.obj (DacaRegsFile)

DacbRegsFile 
*          0    00005c10    00000007     UNINITIALIZED
                  00005c10    00000007     f2838x_GlobalVariableDefs.obj (DacbRegsFile)

DaccRegsFile 
*          0    00005c20    00000007     UNINITIALIZED
                  00005c20    00000007     f2838x_GlobalVariableDefs.obj (DaccRegsFile)

Cmpss1RegsFile 
*          0    00005c80    0000001b     UNINITIALIZED
                  00005c80    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss1RegsFile)

Cmpss2RegsFile 
*          0    00005ca0    0000001b     UNINITIALIZED
                  00005ca0    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss2RegsFile)

Cmpss3RegsFile 
*          0    00005cc0    0000001b     UNINITIALIZED
                  00005cc0    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss3RegsFile)

Cmpss4RegsFile 
*          0    00005ce0    0000001b     UNINITIALIZED
                  00005ce0    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss4RegsFile)

Cmpss5RegsFile 
*          0    00005d00    0000001b     UNINITIALIZED
                  00005d00    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss5RegsFile)

Cmpss6RegsFile 
*          0    00005d20    0000001b     UNINITIALIZED
                  00005d20    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss6RegsFile)

Cmpss7RegsFile 
*          0    00005d40    0000001b     UNINITIALIZED
                  00005d40    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss7RegsFile)

Cmpss8RegsFile 
*          0    00005d60    0000001b     UNINITIALIZED
                  00005d60    0000001b     f2838x_GlobalVariableDefs.obj (Cmpss8RegsFile)

Sdfm1RegsFile 
*          0    00005e00    00000080     UNINITIALIZED
                  00005e00    00000080     f2838x_GlobalVariableDefs.obj (Sdfm1RegsFile)

Sdfm2RegsFile 
*          0    00005e80    00000080     UNINITIALIZED
                  00005e80    00000080     f2838x_GlobalVariableDefs.obj (Sdfm2RegsFile)

McbspaRegsFile 
*          0    00006000    00000024     UNINITIALIZED
                  00006000    00000024     f2838x_GlobalVariableDefs.obj (McbspaRegsFile)

McbspbRegsFile 
*          0    00006040    00000024     UNINITIALIZED
                  00006040    00000024     f2838x_GlobalVariableDefs.obj (McbspbRegsFile)

SpiaRegsFile 
*          0    00006100    00000010     UNINITIALIZED
                  00006100    00000010     f2838x_GlobalVariableDefs.obj (SpiaRegsFile)

SpibRegsFile 
*          0    00006110    00000010     UNINITIALIZED
                  00006110    00000010     f2838x_GlobalVariableDefs.obj (SpibRegsFile)

SpicRegsFile 
*          0    00006120    00000010     UNINITIALIZED
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SpidRegsFile 
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                  000835c1    0000000a     f2838x_defaultisr.obj (.text:_CLA_UNDERFLOW_ISR)
                  000835cb    0000000a     f2838x_defaultisr.obj (.text:_DATALOG_ISR)
                  000835d5    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH1_ISR)
                  000835df    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH2_ISR)
                  000835e9    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH3_ISR)
                  000835f3    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH4_ISR)
                  000835fd    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH5_ISR)
                  00083607    0000000a     f2838x_defaultisr.obj (.text:_DMA_CH6_ISR)
                  00083611    0000000a     f2838x_defaultisr.obj (.text:_ECAP1_ISR)
                  0008361b    0000000a     f2838x_defaultisr.obj (.text:_ECAP2_ISR)
                  00083625    0000000a     f2838x_defaultisr.obj (.text:_ECAP3_ISR)
                  0008362f    0000000a     f2838x_defaultisr.obj (.text:_ECAP4_ISR)
                  00083639    0000000a     f2838x_defaultisr.obj (.text:_ECAP5_ISR)
                  00083643    0000000a     f2838x_defaultisr.obj (.text:_ECAP6_2_ISR)
                  0008364d    0000000a     f2838x_defaultisr.obj (.text:_ECAP6_ISR)
                  00083657    0000000a     f2838x_defaultisr.obj (.text:_ECAP7_2_ISR)
                  00083661    0000000a     f2838x_defaultisr.obj (.text:_ECAP7_ISR)
                  0008366b    0000000a     f2838x_defaultisr.obj (.text:_EMIF_ERROR_ISR)
                  00083675    0000000a     f2838x_defaultisr.obj (.text:_EMU_ISR)
                  0008367f    0000000a     f2838x_defaultisr.obj (.text:_EPWM10_ISR)
                  00083689    0000000a     f2838x_defaultisr.obj (.text:_EPWM10_TZ_ISR)
                  00083693    0000000a     f2838x_defaultisr.obj (.text:_EPWM11_ISR)
                  0008369d    0000000a     f2838x_defaultisr.obj (.text:_EPWM11_TZ_ISR)
                  000836a7    0000000a     f2838x_defaultisr.obj (.text:_EPWM12_ISR)
                  000836b1    0000000a     f2838x_defaultisr.obj (.text:_EPWM12_TZ_ISR)
                  000836bb    0000000a     f2838x_defaultisr.obj (.text:_EPWM1_TZ_ISR)
                  000836c5    0000000a     f2838x_defaultisr.obj (.text:_EPWM2_ISR)
                  000836cf    0000000a     f2838x_defaultisr.obj (.text:_EPWM2_TZ_ISR)
                  000836d9    0000000a     f2838x_defaultisr.obj (.text:_EPWM3_ISR)
                  000836e3    0000000a     f2838x_defaultisr.obj (.text:_EPWM3_TZ_ISR)
                  000836ed    0000000a     f2838x_defaultisr.obj (.text:_EPWM4_ISR)
                  000836f7    0000000a     f2838x_defaultisr.obj (.text:_EPWM4_TZ_ISR)
                  00083701    0000000a     f2838x_defaultisr.obj (.text:_EPWM5_ISR)
                  0008370b    0000000a     f2838x_defaultisr.obj (.text:_EPWM5_TZ_ISR)
                  00083715    0000000a     f2838x_defaultisr.obj (.text:_EPWM6_ISR)
                  0008371f    0000000a     f2838x_defaultisr.obj (.text:_EPWM6_TZ_ISR)
                  00083729    0000000a     f2838x_defaultisr.obj (.text:_EPWM7_ISR)
                  00083733    0000000a     f2838x_defaultisr.obj (.text:_EPWM7_TZ_ISR)
                  0008373d    0000000a     f2838x_defaultisr.obj (.text:_EPWM8_ISR)
                  00083747    0000000a     f2838x_defaultisr.obj (.text:_EPWM8_TZ_ISR)
                  00083751    0000000a     f2838x_defaultisr.obj (.text:_EPWM9_ISR)
                  0008375b    0000000a     f2838x_defaultisr.obj (.text:_EPWM9_TZ_ISR)
                  00083765    0000000a     f2838x_defaultisr.obj (.text:_EQEP1_ISR)
                  0008376f    0000000a     f2838x_defaultisr.obj (.text:_EQEP2_ISR)
                  00083779    0000000a     f2838x_defaultisr.obj (.text:_EQEP3_ISR)
                  00083783    0000000a     f2838x_defaultisr.obj (.text:_FPU_OFLOW_ISR)
                  0008378d    0000000a     f2838x_defaultisr.obj (.text:_FPU_UFLOW_ISR)
                  00083797    0000000a     f2838x_defaultisr.obj (.text:_I2CA_FIFO_ISR)
                  000837a1    0000000a     f2838x_defaultisr.obj (.text:_I2CA_ISR)
                  000837ab    0000000a     f2838x_defaultisr.obj (.text:_I2CB_FIFO_ISR)
                  000837b5    0000000a     f2838x_defaultisr.obj (.text:_I2CB_ISR)
                  000837bf    0000000a     f2838x_defaultisr.obj (.text:_ILLEGAL_ISR)
                  000837c9    0000000a     f2838x_defaultisr.obj (.text:_MCBSPA_RX_ISR)
                  000837d3    0000000a     f2838x_defaultisr.obj (.text:_MCBSPA_TX_ISR)
                  000837dd    0000000a     f2838x_defaultisr.obj (.text:_MCBSPB_RX_ISR)
                  000837e7    0000000a     f2838x_defaultisr.obj (.text:_MCBSPB_TX_ISR)
                  000837f1    0000000a     f2838x_defaultisr.obj (.text:_NMI_ISR)
                  000837fb    0000000a     f2838x_defaultisr.obj (.text:_NOTUSED_ISR)
                  00083805    0000000a     f2838x_defaultisr.obj (.text:_PIE_RESERVED_ISR)
                  0008380f    0000000a     f2838x_defaultisr.obj (.text:_RTOS_ISR)
                  00083819    0000000a     f2838x_defaultisr.obj (.text:_SCIA_RX_ISR)
                  00083823    0000000a     f2838x_defaultisr.obj (.text:_SCIA_TX_ISR)
                  0008382d    0000000a     f2838x_defaultisr.obj (.text:_SCIB_RX_ISR)
                  00083837    0000000a     f2838x_defaultisr.obj (.text:_SCIB_TX_ISR)
                  00083841    0000000a     f2838x_defaultisr.obj (.text:_SCIC_RX_ISR)
                  0008384b    0000000a     f2838x_defaultisr.obj (.text:_SCIC_TX_ISR)
                  00083855    0000000a     f2838x_defaultisr.obj (.text:_SCID_RX_ISR)
                  0008385f    0000000a     f2838x_defaultisr.obj (.text:_SCID_TX_ISR)
                  00083869    0000000a     f2838x_defaultisr.obj (.text:_SDFM1_ISR)
                  00083873    0000000a     f2838x_defaultisr.obj (.text:_SDFM2_ISR)
                  0008387d    0000000a     f2838x_defaultisr.obj (.text:_SPIA_RX_ISR)
                  00083887    0000000a     f2838x_defaultisr.obj (.text:_SPIA_TX_ISR)
                  00083891    0000000a     f2838x_defaultisr.obj (.text:_SPIB_RX_ISR)
                  0008389b    0000000a     f2838x_defaultisr.obj (.text:_SPIB_TX_ISR)
                  000838a5    0000000a     f2838x_defaultisr.obj (.text:_SPIC_RX_ISR)
                  000838af    0000000a     f2838x_defaultisr.obj (.text:_SPIC_TX_ISR)
                  000838b9    0000000a     f2838x_defaultisr.obj (.text:_TIMER0_ISR)
                  000838c3    0000000a     f2838x_defaultisr.obj (.text:_TIMER1_ISR)
                  000838cd    0000000a     f2838x_defaultisr.obj (.text:_TIMER2_ISR)
                  000838d7    0000000a     f2838x_defaultisr.obj (.text:_USBA_ISR)
                  000838e1    0000000a     f2838x_defaultisr.obj (.text:_USER10_ISR)
                  000838eb    0000000a     f2838x_defaultisr.obj (.text:_USER11_ISR)
                  000838f5    0000000a     f2838x_defaultisr.obj (.text:_USER12_ISR)
                  000838ff    0000000a     f2838x_defaultisr.obj (.text:_USER1_ISR)
                  00083909    0000000a     f2838x_defaultisr.obj (.text:_USER2_ISR)
                  00083913    0000000a     f2838x_defaultisr.obj (.text:_USER3_ISR)
                  0008391d    0000000a     f2838x_defaultisr.obj (.text:_USER4_ISR)
                  00083927    0000000a     f2838x_defaultisr.obj (.text:_USER5_ISR)
                  00083931    0000000a     f2838x_defaultisr.obj (.text:_USER6_ISR)
                  0008393b    0000000a     f2838x_defaultisr.obj (.text:_USER7_ISR)
                  00083945    0000000a     f2838x_defaultisr.obj (.text:_USER8_ISR)
                  0008394f    0000000a     f2838x_defaultisr.obj (.text:_USER9_ISR)
                  00083959    0000000a     f2838x_defaultisr.obj (.text:_WAKE_ISR)
                  00083963    0000000a     f2838x_defaultisr.obj (.text:_XINT1_ISR)
                  0008396d    0000000a     f2838x_defaultisr.obj (.text:_XINT2_ISR)
                  00083977    0000000a     f2838x_defaultisr.obj (.text:_XINT3_ISR)
                  00083981    0000000a     f2838x_defaultisr.obj (.text:_XINT4_ISR)
                  0008398b    0000000a     f2838x_defaultisr.obj (.text:_XINT5_ISR)
                  00083995    00000009     f2838x_piectrl.obj (.text:_EnableInterrupts)
                  0008399e    00000009     rts2800_fpu32.lib : _lock.c.obj (.text)
                  000839a7    00000007     SetInterrupts.obj (.text:_SetInterrupts)
                  000839ae    00000002     rts2800_fpu32.lib : pre_init.c.obj (.text)
                  000839b0    00000001                       : startup.c.obj (.text)

.econst    0    0008801c    000001c0     
                  0008801c    000001c0     f2838x_pievect.obj (.econst:_PieVectTableInit)

MODULE SUMMARY

       Module                            code   initialized data   uninitialized data
       ------                            ----   ----------------   ------------------
    .\
       f2838x_GlobalVariableDefs.obj     0      0                  13199             
       f2838x_defaultisr.obj             2273   0                  0                 
       Xbar.obj                          2113   0                  0                 
       Gpio.obj                          953    0                  0                 
       f2838x_pievect.obj                34     448                0                 
       EPwm.obj                          292    0                  0                 
       SysCtrl.obj                       247    0                  0                 
       f2838x_adc.obj                    244    0                  0                 
       Adc.obj                           95     0                  0                 
       f2838x_piectrl.obj                40     0                  0                 
       Main.obj                          29     0                  0                 
       interrupt_EPwm1_latency_isr.obj   16     0                  0                 
       Watchdog.obj                      12     0                  0                 
       SetInterrupts.obj                 7      0                  0                 
       F2838x_CodeStartBranch.obj        2      0                  0                 
    +--+---------------------------------+------+------------------+--------------------+
       Total:                            6357   448                13199             
                                                                                     
    C:\ti\ccs920\ccs\tools\compiler\ti-cgt-C2000_21.6.0.LTS\lib\rts2800_fpu32.lib
       boot28.asm.obj                    86     0                  0                 
       exit.c.obj                        41     14                 6                 
       cpy_tbl.c.obj                     36     0                  0                 
       memcpy.c.obj                      29     0                  0                 
       _lock.c.obj                       9      10                 4                 
       args_main.c.obj                   18     0                  0                 
       pre_init.c.obj                    2      0                  0                 
       startup.c.obj                     1      0                  0                 
    +--+---------------------------------+------+------------------+--------------------+
       Total:                            222    24                 10                
                                                                                     
       Stack:                            0      0                  512               
    +--+---------------------------------+------+------------------+--------------------+
       Grand Total:                      6579   472                13721             


GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE

address     data page           name
--------    ----------------    ----
00000400      10 (00000400)     __stack

00000b00      2c (00000b00)     _AdcaResultRegs
00000b20      2c (00000b00)     _AdcbResultRegs

00000b40      2d (00000b40)     _AdccResultRegs
00000b60      2d (00000b40)     _AdcdResultRegs

00000c00      30 (00000c00)     _CpuTimer0Regs
00000c08      30 (00000c00)     _CpuTimer1Regs
00000c10      30 (00000c00)     _CpuTimer2Regs

00000ce0      33 (00000cc0)     _PieCtrlRegs

00000d00      34 (00000d00)     _EmuBMode
00000d00      34 (00000d00)     _PieVectTable
00000d01      34 (00000d00)     _EmuBootPins

00001000      40 (00001000)     _DmaRegs

00001400      50 (00001400)     _Cla1Regs

00004000     100 (00004000)     _EPwm1Regs

00004100     104 (00004100)     _EPwm2Regs

00004200     108 (00004200)     _EPwm3Regs

00004300     10c (00004300)     _EPwm4Regs

00004400     110 (00004400)     _EPwm5Regs

00004500     114 (00004500)     _EPwm6Regs

00004600     118 (00004600)     _EPwm7Regs

00004700     11c (00004700)     _EPwm8Regs

00004800     120 (00004800)     _EPwm9Regs

00004900     124 (00004900)     _EPwm10Regs

00004a00     128 (00004a00)     _EPwm11Regs

00004b00     12c (00004b00)     _EPwm12Regs

00004c00     130 (00004c00)     _EPwm13Regs

00004d00     134 (00004d00)     _EPwm14Regs

00004e00     138 (00004e00)     _EPwm15Regs

00004f00     13c (00004f00)     _EPwm16Regs

00005100     144 (00005100)     _EQep1Regs

00005140     145 (00005140)     _EQep2Regs

00005180     146 (00005180)     _EQep3Regs

00005200     148 (00005200)     _ECap1Regs

00005240     149 (00005240)     _ECap2Regs

00005280     14a (00005280)     _ECap3Regs

000052c0     14b (000052c0)     _ECap4Regs

00005300     14c (00005300)     _ECap5Regs

00005340     14d (00005340)     _ECap6Regs
00005360     14d (00005340)     _HRCap6Regs

00005380     14e (00005380)     _ECap7Regs
000053a0     14e (00005380)     _HRCap7Regs

00005c00     170 (00005c00)     _DacaRegs
00005c10     170 (00005c00)     _DacbRegs
00005c20     170 (00005c00)     _DaccRegs

00005c80     172 (00005c80)     _Cmpss1Regs
00005ca0     172 (00005c80)     _Cmpss2Regs

00005cc0     173 (00005cc0)     _Cmpss3Regs
00005ce0     173 (00005cc0)     _Cmpss4Regs

00005d00     174 (00005d00)     _Cmpss5Regs
00005d20     174 (00005d00)     _Cmpss6Regs

00005d40     175 (00005d40)     _Cmpss7Regs
00005d60     175 (00005d40)     _Cmpss8Regs

00005e00     178 (00005e00)     _Sdfm1Regs

00005e80     17a (00005e80)     _Sdfm2Regs

00006000     180 (00006000)     _McbspaRegs

00006040     181 (00006040)     _McbspbRegs

00006100     184 (00006100)     _SpiaRegs
00006110     184 (00006100)     _SpibRegs
00006120     184 (00006100)     _SpicRegs
00006130     184 (00006100)     _SpidRegs

00006340     18d (00006340)     _BgcrcCpuRegs

00006380     18e (00006380)     _BgcrcCla1Regs

00006400     190 (00006400)     _PmbusaRegs

00006600     198 (00006600)     _FsiTxaRegs

00006680     19a (00006680)     _FsiRxaRegs

00006700     19c (00006700)     _FsiTxbRegs

00006780     19e (00006780)     _FsiRxbRegs

00006880     1a2 (00006880)     _FsiRxcRegs

00006980     1a6 (00006980)     _FsiRxdRegs

00006a80     1aa (00006a80)     _FsiRxeRegs

00006b80     1ae (00006b80)     _FsiRxfRegs

00006c80     1b2 (00006c80)     _FsiRxgRegs

00006d80     1b6 (00006d80)     _FsiRxhRegs

00007000     1c0 (00007000)     _WdRegs

00007060     1c1 (00007040)     _NmiIntruptRegs
00007070     1c1 (00007040)     _XintRegs

00007200     1c8 (00007200)     _SciaRegs
00007210     1c8 (00007200)     _ScibRegs
00007220     1c8 (00007200)     _ScicRegs
00007230     1c8 (00007200)     _ScidRegs

00007300     1cc (00007300)     _I2caRegs

00007340     1cd (00007340)     _I2cbRegs

00007400     1d0 (00007400)     _AdcaRegs

00007480     1d2 (00007480)     _AdcbRegs

00007500     1d4 (00007500)     _AdccRegs

00007580     1d6 (00007580)     _AdcdRegs

00007900     1e4 (00007900)     _InputXbarRegs
00007920     1e4 (00007900)     _XbarRegs

00007940     1e5 (00007940)     _SyncSocRegs

00007980     1e6 (00007980)     _DmaClaSrcSelRegs

00007a00     1e8 (00007a00)     _EPwmXbarRegs

00007a80     1ea (00007a80)     _OutputXbarRegs

00007c00     1f0 (00007c00)     _GpioCtrlRegs

00007f00     1fc (00007f00)     _GpioDataRegs

0000a800     2a0 (0000a800)     ___TI_enable_exit_profile_output
0000a802     2a0 (0000a800)     ___TI_cleanup_ptr
0000a804     2a0 (0000a800)     ___TI_dtors_ptr
0000a806     2a0 (0000a800)     __lock
0000a808     2a0 (0000a800)     __unlock

00047000    11c0 (00047000)     _Emif1Regs

00047800    11e0 (00047800)     _Emif2Regs

00048000    1200 (00048000)     _CanaRegs

0004a000    1280 (0004a000)     _CanbRegs

00057e00    15f8 (00057e00)     _EcatssRegs

00057f00    15fc (00057f00)     _EcatssConfigRegs

0005c400    1710 (0005c400)     _McanssRegs

0005c600    1718 (0005c600)     _McanRegs

0005c800    1720 (0005c800)     _McanErrorRegs

0005ce00    1738 (0005ce00)     _Cpu1toCpu2IpcRegs

0005ce40    1739 (0005ce40)     _Cpu1toCmIpcRegs

0005d000    1740 (0005d000)     _DevCfgRegs

0005d200    1748 (0005d200)     _ClkCfgRegs

0005d300    174c (0005d300)     _CpuSysRegs

0005d400    1750 (0005d400)     _SysStatusRegs

0005d500    1754 (0005d500)     _SysPeriphAcRegs

0005d700    175c (0005d700)     _AnalogSubsysRegs

0005dc00    1770 (0005dc00)     _CmConfRegs

0005e000    1780 (0005e000)     _HwbistRegs

0005e700    179c (0005e700)     _Dcc0Regs

0005e740    179d (0005e740)     _Dcc1Regs

0005e780    179e (0005e780)     _Dcc2Regs

0005e800    17a0 (0005e800)     _EradGlobalRegs

0005e900    17a4 (0005e900)     _EradHwbpRegs

0005e980    17a6 (0005e980)     _EradCounterRegs

0005ea00    17a8 (0005ea00)     _EradCrcRegs

0005f000    17c0 (0005f000)     _DcsmZ1Regs

0005f080    17c2 (0005f080)     _DcsmZ2Regs

0005f0c0    17c3 (0005f0c0)     _DcsmCommonRegs

0005f400    17d0 (0005f400)     _MemCfgRegs

0005f4c0    17d3 (0005f4c0)     _Emif1ConfigRegs
0005f4e0    17d3 (0005f4c0)     _Emif2ConfigRegs

0005f500    17d4 (0005f500)     _AccessProtectionRegs

0005f540    17d5 (0005f540)     _MemoryErrorRegs

0005f580    17d6 (0005f580)     _RomWaitStateRegs
0005f588    17d6 (0005f580)     _RomPrefetchRegs
0005f590    17d6 (0005f580)     _TestErrorRegs

0005f800    17e0 (0005f800)     _Flash0CtrlRegs

0005fb00    17ec (0005fb00)     _Flash0EccRegs

00078000    1e00 (00078000)     _DcsmZ1Otp

00078200    1e08 (00078200)     _DcsmZ2Otp

0008801c    2200 (00088000)     _PieVectTableInit


GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name 

page  address   name                            
----  -------   ----                            
abs   ffffffff  .text                           
0     00082fb1  C$$EXIT                         
0     0008344f  _ADCA1_ISR                      
0     00083459  _ADCA2_ISR                      
0     00083463  _ADCA3_ISR                      
0     0008346d  _ADCA4_ISR                      
0     00083477  _ADCA_EVT_ISR                   
0     00083481  _ADCB1_ISR                      
0     0008348b  _ADCB2_ISR                      
0     00083495  _ADCB3_ISR                      
0     0008349f  _ADCB4_ISR                      
0     000834a9  _ADCB_EVT_ISR                   
0     000834b3  _ADCC1_ISR                      
0     000834bd  _ADCC2_ISR                      
0     000834c7  _ADCC3_ISR                      
0     000834d1  _ADCC4_ISR                      
0     000834db  _ADCC_EVT_ISR                   
0     000834e5  _ADCD1_ISR                      
0     000834ef  _ADCD2_ISR                      
0     000834f9  _ADCD3_ISR                      
0     00083503  _ADCD4_ISR                      
0     0008350d  _ADCD_EVT_ISR                   
0     0005f500  _AccessProtectionRegs           
0     00082e08  _AdcSetMode                     
0     00007400  _AdcaRegs                       
0     00000b00  _AdcaResultRegs                 
0     00007480  _AdcbRegs                       
0     00000b20  _AdcbResultRegs                 
0     00007500  _AdccRegs                       
0     00000b40  _AdccResultRegs                 
0     00007580  _AdcdRegs                       
0     00000b60  _AdcdResultRegs                 
0     0005d700  _AnalogSubsysRegs               
0     00006380  _BgcrcCla1Regs                  
0     00006340  _BgcrcCpuRegs                   
0     00083517  _CANA0_ISR                      
0     00083521  _CANA1_ISR                      
0     0008352b  _CANB0_ISR                      
0     00083535  _CANB1_ISR                      
0     0008353f  _CIPC0_ISR                      
0     00083549  _CIPC1_ISR                      
0     00083553  _CIPC2_ISR                      
0     0008355d  _CIPC3_ISR                      
0     0008309b  _CLA1CRC_INT_ISR                
0     00083567  _CLA1_1_ISR                     
0     00083571  _CLA1_2_ISR                     
0     0008357b  _CLA1_3_ISR                     
0     00083585  _CLA1_4_ISR                     
0     0008358f  _CLA1_5_ISR                     
0     00083599  _CLA1_6_ISR                     
0     000835a3  _CLA1_7_ISR                     
0     000835ad  _CLA1_8_ISR                     
0     000835b7  _CLA_OVERFLOW_ISR               
0     000835c1  _CLA_UNDERFLOW_ISR              
0     000830a8  _CLB1_ISR                       
0     000830b5  _CLB2_ISR                       
0     000830c2  _CLB3_ISR                       
0     000830cf  _CLB4_ISR                       
0     000830dc  _CLB5_ISR                       
0     000830e9  _CLB6_ISR                       
0     000830f6  _CLB7_ISR                       
0     00083103  _CLB8_ISR                       
0     00083110  _CMTOCPUXIPC0_ISR               
0     0008311d  _CMTOCPUXIPC1_ISR               
0     0008312a  _CMTOCPUXIPC2_ISR               
0     00083137  _CMTOCPUXIPC3_ISR               
0     00083144  _CMTOCPUXIPC4_ISR               
0     00083151  _CMTOCPUXIPC5_ISR               
0     0008315e  _CMTOCPUXIPC6_ISR               
0     0008316b  _CMTOCPUXIPC7_ISR               
0     00083178  _CM_STATUS_ISR                  
0     00083185  _CPUCRC_INT_ISR                 
0     00082f74  _CalAdcINL                      
0     00048000  _CanaRegs                       
0     0004a000  _CanbRegs                       
0     00001400  _Cla1Regs                       
0     0005d200  _ClkCfgRegs                     
0     0005dc00  _CmConfRegs                     
0     00005c80  _Cmpss1Regs                     
0     00005ca0  _Cmpss2Regs                     
0     00005cc0  _Cmpss3Regs                     
0     00005ce0  _Cmpss4Regs                     
0     00005d00  _Cmpss5Regs                     
0     00005d20  _Cmpss6Regs                     
0     00005d40  _Cmpss7Regs                     
0     00005d60  _Cmpss8Regs                     
0     0005ce40  _Cpu1toCmIpcRegs                
0     0005ce00  _Cpu1toCpu2IpcRegs              
0     0005d300  _CpuSysRegs                     
0     00000c00  _CpuTimer0Regs                  
0     00000c08  _CpuTimer1Regs                  
0     00000c10  _CpuTimer2Regs                  
0     000835cb  _DATALOG_ISR                    
0     000835d5  _DMA_CH1_ISR                    
0     000835df  _DMA_CH2_ISR                    
0     000835e9  _DMA_CH3_ISR                    
0     000835f3  _DMA_CH4_ISR                    
0     000835fd  _DMA_CH5_ISR                    
0     00083607  _DMA_CH6_ISR                    
0     00005c00  _DacaRegs                       
0     00005c10  _DacbRegs                       
0     00005c20  _DaccRegs                       
0     0005e700  _Dcc0Regs                       
0     0005e740  _Dcc1Regs                       
0     0005e780  _Dcc2Regs                       
0     0005f0c0  _DcsmCommonRegs                 
0     00078000  _DcsmZ1Otp                      
0     0005f000  _DcsmZ1Regs                     
0     00078200  _DcsmZ2Otp                      
0     0005f080  _DcsmZ2Regs                     
0     0005d000  _DevCfgRegs                     
0     00007980  _DmaClaSrcSelRegs               
0     00001000  _DmaRegs                        
0     00083611  _ECAP1_ISR                      
0     0008361b  _ECAP2_ISR                      
0     00083625  _ECAP3_ISR                      
0     0008362f  _ECAP4_ISR                      
0     00083639  _ECAP5_ISR                      
0     00083643  _ECAP6_2_ISR                    
0     0008364d  _ECAP6_ISR                      
0     00083657  _ECAP7_2_ISR                    
0     00083661  _ECAP7_ISR                      
0     00083192  _ECATRSTINTN_ISR                
0     0008319f  _ECATSYNC0_ISR                  
0     000831ac  _ECATSYNC1_ISR                  
0     000831b9  _ECAT_ISR                       
0     00005200  _ECap1Regs                      
0     00005240  _ECap2Regs                      
0     00005280  _ECap3Regs                      
0     000052c0  _ECap4Regs                      
0     00005300  _ECap5Regs                      
0     00005340  _ECap6Regs                      
0     00005380  _ECap7Regs                      
0     0008366b  _EMIF_ERROR_ISR                 
0     000831c6  _EMPTY_ISR                      
0     00083675  _EMU_ISR                        
0     0008367f  _EPWM10_ISR                     
0     00083689  _EPWM10_TZ_ISR                  
0     00083693  _EPWM11_ISR                     
0     0008369d  _EPWM11_TZ_ISR                  
0     000836a7  _EPWM12_ISR                     
0     000836b1  _EPWM12_TZ_ISR                  
0     000831d3  _EPWM13_ISR                     
0     000831e0  _EPWM13_TZ_ISR                  
0     000831ed  _EPWM14_ISR                     
0     000831fa  _EPWM14_TZ_ISR                  
0     00083207  _EPWM15_ISR                     
0     00083214  _EPWM15_TZ_ISR                  
0     00083221  _EPWM16_ISR                     
0     0008322e  _EPWM16_TZ_ISR                  
0     0008308b  _EPWM1_ISR                      
0     000836bb  _EPWM1_TZ_ISR                   
0     000836c5  _EPWM2_ISR                      
0     000836cf  _EPWM2_TZ_ISR                   
0     000836d9  _EPWM3_ISR                      
0     000836e3  _EPWM3_TZ_ISR                   
0     000836ed  _EPWM4_ISR                      
0     000836f7  _EPWM4_TZ_ISR                   
0     00083701  _EPWM5_ISR                      
0     0008370b  _EPWM5_TZ_ISR                   
0     00083715  _EPWM6_ISR                      
0     0008371f  _EPWM6_TZ_ISR                   
0     00083729  _EPWM7_ISR                      
0     00083733  _EPWM7_TZ_ISR                   
0     0008373d  _EPWM8_ISR                      
0     00083747  _EPWM8_TZ_ISR                   
0     00083751  _EPWM9_ISR                      
0     0008375b  _EPWM9_TZ_ISR                   
0     00004900  _EPwm10Regs                     
0     00004a00  _EPwm11Regs                     
0     00004b00  _EPwm12Regs                     
0     00004c00  _EPwm13Regs                     
0     00004d00  _EPwm14Regs                     
0     00004e00  _EPwm15Regs                     
0     00004f00  _EPwm16Regs                     
0     00004000  _EPwm1Regs                      
0     00004100  _EPwm2Regs                      
0     00004200  _EPwm3Regs                      
0     00004300  _EPwm4Regs                      
0     00004400  _EPwm5Regs                      
0     00004500  _EPwm6Regs                      
0     00004600  _EPwm7Regs                      
0     00004700  _EPwm8Regs                      
0     00004800  _EPwm9Regs                      
0     00007a00  _EPwmXbarRegs                   
0     00083765  _EQEP1_ISR                      
0     0008376f  _EQEP2_ISR                      
0     00083779  _EQEP3_ISR                      
0     00005100  _EQep1Regs                      
0     00005140  _EQep2Regs                      
0     00005180  _EQep3Regs                      
0     00057f00  _EcatssConfigRegs               
0     00057e00  _EcatssRegs                     
0     0005f4c0  _Emif1ConfigRegs                
0     00047000  _Emif1Regs                      
0     0005f4e0  _Emif2ConfigRegs                
0     00047800  _Emif2Regs                      
0     00000d00  _EmuBMode                       
0     00000d01  _EmuBootPins                    
0     00083995  _EnableInterrupts               
0     0005e980  _EradCounterRegs                
0     0005ea00  _EradCrcRegs                    
0     0005e800  _EradGlobalRegs                 
0     0005e900  _EradHwbpRegs                   
0     0008323b  _FMC_ISR                        
0     00083783  _FPU_OFLOW_ISR                  
0     0008378d  _FPU_UFLOW_ISR                  
0     00083248  _FSIRXA1_ISR                    
0     00083255  _FSIRXA2_ISR                    
0     00083262  _FSIRXB1_ISR                    
0     0008326f  _FSIRXB2_ISR                    
0     0008327c  _FSIRXC1_ISR                    
0     00083289  _FSIRXC2_ISR                    
0     00083296  _FSIRXD1_ISR                    
0     000832a3  _FSIRXD2_ISR                    
0     000832b0  _FSIRXE1_ISR                    
0     000832bd  _FSIRXE2_ISR                    
0     000832ca  _FSIRXF1_ISR                    
0     000832d7  _FSIRXF2_ISR                    
0     000832e4  _FSIRXG1_ISR                    
0     000832f1  _FSIRXG2_ISR                    
0     000832fe  _FSIRXH1_ISR                    
0     0008330b  _FSIRXH2_ISR                    
0     00083318  _FSITXA1_ISR                    
0     00083325  _FSITXA2_ISR                    
0     00083332  _FSITXB1_ISR                    
0     0008333f  _FSITXB2_ISR                    
0     0005f800  _Flash0CtrlRegs                 
0     0005fb00  _Flash0EccRegs                  
0     00006680  _FsiRxaRegs                     
0     00006780  _FsiRxbRegs                     
0     00006880  _FsiRxcRegs                     
0     00006980  _FsiRxdRegs                     
0     00006a80  _FsiRxeRegs                     
0     00006b80  _FsiRxfRegs                     
0     00006c80  _FsiRxgRegs                     
0     00006d80  _FsiRxhRegs                     
0     00006600  _FsiTxaRegs                     
0     00006700  _FsiTxbRegs                     
0     00007c00  _GpioCtrlRegs                   
0     00007f00  _GpioDataRegs                   
0     00005360  _HRCap6Regs                     
0     000053a0  _HRCap7Regs                     
0     0005e000  _HwbistRegs                     
0     00083797  _I2CA_FIFO_ISR                  
0     0008334c  _I2CA_HIGH_ISR                  
0     000837a1  _I2CA_ISR                       
0     000837ab  _I2CB_FIFO_ISR                  
0     000837b5  _I2CB_ISR                       
0     00007300  _I2caRegs                       
0     00007340  _I2cbRegs                       
0     000837bf  _ILLEGAL_ISR                    
0     00082ebf  _InitAdca                       
0     00082bfa  _InitEPwm                       
0     00082841  _InitGpio                       
0     00083020  _InitPieCtrl                    
0     00082ffe  _InitPieVectTable               
0     00082d11  _InitSysCtrl                    
0     00083443  _InitWatchdog                   
0     00082000  _InitXbar                       
0     00007900  _InputXbarRegs                  
0     00083359  _MCANSS0_ISR                    
0     00083366  _MCANSS1_ISR                    
0     00083373  _MCANSS_ECC_CORR_PLS_ISR        
0     00083380  _MCANSS_WAKE_AND_TS_PLS_ISR     
0     000837c9  _MCBSPA_RX_ISR                  
0     000837d3  _MCBSPA_TX_ISR                  
0     000837dd  _MCBSPB_RX_ISR                  
0     000837e7  _MCBSPB_TX_ISR                  
0     0005c800  _McanErrorRegs                  
0     0005c600  _McanRegs                       
0     0005c400  _McanssRegs                     
0     00006000  _McbspaRegs                     
0     00006040  _McbspbRegs                     
0     0005f400  _MemCfgRegs                     
0     0005f540  _MemoryErrorRegs                
0     000837f1  _NMI_ISR                        
0     000837fb  _NOTUSED_ISR                    
0     00007060  _NmiIntruptRegs                 
0     00007a80  _OutputXbarRegs                 
0     0008338d  _PBIST_ISR                      
0     00083805  _PIE_RESERVED_ISR               
0     0008339a  _PMBUSA_ISR                     
0     00000ce0  _PieCtrlRegs                    
0     00000d00  _PieVectTable                   
0     0008801c  _PieVectTableInit               
0     00006400  _PmbusaRegs                     
0     000833a7  _PwmViennaOn                    
0     0008380f  _RTOS_ISR                       
0     00008000  _RamfuncsLoadEnd                
abs   00000000  _RamfuncsLoadSize               
0     00008000  _RamfuncsLoadStart              
0     00008000  _RamfuncsRunEnd                 
abs   00000000  _RamfuncsRunSize                
0     00008000  _RamfuncsRunStart               
0     0005f588  _RomPrefetchRegs                
0     0005f580  _RomWaitStateRegs               
0     00083819  _SCIA_RX_ISR                    
0     00083823  _SCIA_TX_ISR                    
0     0008382d  _SCIB_RX_ISR                    
0     00083837  _SCIB_TX_ISR                    
0     00083841  _SCIC_RX_ISR                    
0     0008384b  _SCIC_TX_ISR                    
0     00083855  _SCID_RX_ISR                    
0     0008385f  _SCID_TX_ISR                    
0     000833b4  _SDFM1DR1_ISR                   
0     000833c1  _SDFM1DR2_ISR                   
0     000833ce  _SDFM1DR3_ISR                   
0     000833db  _SDFM1DR4_ISR                   
0     00083869  _SDFM1_ISR                      
0     000833e8  _SDFM2DR1_ISR                   
0     000833f5  _SDFM2DR2_ISR                   
0     00083402  _SDFM2DR3_ISR                   
0     0008340f  _SDFM2DR4_ISR                   
0     00083873  _SDFM2_ISR                      
0     0008387d  _SPIA_RX_ISR                    
0     00083887  _SPIA_TX_ISR                    
0     00083891  _SPIB_RX_ISR                    
0     0008389b  _SPIB_TX_ISR                    
0     000838a5  _SPIC_RX_ISR                    
0     000838af  _SPIC_TX_ISR                    
0     0008341c  _SPID_RX_ISR                    
0     00083429  _SPID_TX_ISR                    
0     00083436  _SYS_ERR_ISR                    
0     00007200  _SciaRegs                       
0     00007210  _ScibRegs                       
0     00007220  _ScicRegs                       
0     00007230  _ScidRegs                       
0     00005e00  _Sdfm1Regs                      
0     00005e80  _Sdfm2Regs                      
0     000839a7  _SetInterrupts                  
0     00006100  _SpiaRegs                       
0     00006110  _SpibRegs                       
0     00006120  _SpicRegs                       
0     00006130  _SpidRegs                       
0     00007940  _SyncSocRegs                    
0     0005d500  _SysPeriphAcRegs                
0     0005d400  _SysStatusRegs                  
0     000838b9  _TIMER0_ISR                     
0     000838c3  _TIMER1_ISR                     
0     000838cd  _TIMER2_ISR                     
0     0005f590  _TestErrorRegs                  
0     000838d7  _USBA_ISR                       
0     000838e1  _USER10_ISR                     
0     000838eb  _USER11_ISR                     
0     000838f5  _USER12_ISR                     
0     000838ff  _USER1_ISR                      
0     00083909  _USER2_ISR                      
0     00083913  _USER3_ISR                      
0     0008391d  _USER4_ISR                      
0     00083927  _USER5_ISR                      
0     00083931  _USER6_ISR                      
0     0008393b  _USER7_ISR                      
0     00083945  _USER8_ISR                      
0     0008394f  _USER9_ISR                      
0     00083959  _WAKE_ISR                       
0     00007000  _WdRegs                         
0     00083963  _XINT1_ISR                      
0     0008396d  _XINT2_ISR                      
0     00083977  _XINT3_ISR                      
0     00083981  _XINT4_ISR                      
0     0008398b  _XINT5_ISR                      
0     00007920  _XbarRegs                       
0     00007070  _XintRegs                       
0     00000600  __STACK_END                     
abs   00000200  __STACK_SIZE                    
0     0000a802  ___TI_cleanup_ptr               
0     0000a804  ___TI_dtors_ptr                 
0     0000a800  ___TI_enable_exit_profile_output
abs   ffffffff  ___TI_pprof_out_hndl            
abs   ffffffff  ___TI_prof_data_size            
abs   ffffffff  ___TI_prof_data_start           
abs   ffffffff  ___binit__                      
abs   ffffffff  ___c_args__                     
0     00088000  ___cinit__                      
abs   ffffffff  ___etext__                      
abs   ffffffff  ___pinit__                      
abs   ffffffff  ___text__                       
0     00083079  __args_main                     
0     0000a806  __lock                          
0     000839a6  __nop                           
0     000839a2  __register_lock                 
0     0008399e  __register_unlock               
0     00000400  __stack                         
0     000839b0  __system_post_cinit             
0     000839ae  __system_pre_init               
0     0000a808  __unlock                        
0     00082fb1  _abort                          
0     00082f1e  _c_int00                        
0     00082fda  _copy_in                        
0     00082fb3  _exit                           
0     0008303f  _main                           
0     0008305c  _memcpy                         
abs   ffffffff  binit                           
0     00088000  cinit                           
0     00080000  code_start                      
abs   ffffffff  etext                           
abs   ffffffff  pinit                           


GLOBAL SYMBOLS: SORTED BY Symbol Address 

page  address   name                            
----  -------   ----                            
0     00000400  __stack                         
0     00000600  __STACK_END                     
0     00000b00  _AdcaResultRegs                 
0     00000b20  _AdcbResultRegs                 
0     00000b40  _AdccResultRegs                 
0     00000b60  _AdcdResultRegs                 
0     00000c00  _CpuTimer0Regs                  
0     00000c08  _CpuTimer1Regs                  
0     00000c10  _CpuTimer2Regs                  
0     00000ce0  _PieCtrlRegs                    
0     00000d00  _EmuBMode                       
0     00000d00  _PieVectTable                   
0     00000d01  _EmuBootPins                    
0     00001000  _DmaRegs                        
0     00001400  _Cla1Regs                       
0     00004000  _EPwm1Regs                      
0     00004100  _EPwm2Regs                      
0     00004200  _EPwm3Regs                      
0     00004300  _EPwm4Regs                      
0     00004400  _EPwm5Regs                      
0     00004500  _EPwm6Regs                      
0     00004600  _EPwm7Regs                      
0     00004700  _EPwm8Regs                      
0     00004800  _EPwm9Regs                      
0     00004900  _EPwm10Regs                     
0     00004a00  _EPwm11Regs                     
0     00004b00  _EPwm12Regs                     
0     00004c00  _EPwm13Regs                     
0     00004d00  _EPwm14Regs                     
0     00004e00  _EPwm15Regs                     
0     00004f00  _EPwm16Regs                     
0     00005100  _EQep1Regs                      
0     00005140  _EQep2Regs                      
0     00005180  _EQep3Regs                      
0     00005200  _ECap1Regs                      
0     00005240  _ECap2Regs                      
0     00005280  _ECap3Regs                      
0     000052c0  _ECap4Regs                      
0     00005300  _ECap5Regs                      
0     00005340  _ECap6Regs                      
0     00005360  _HRCap6Regs                     
0     00005380  _ECap7Regs                      
0     000053a0  _HRCap7Regs                     
0     00005c00  _DacaRegs                       
0     00005c10  _DacbRegs                       
0     00005c20  _DaccRegs                       
0     00005c80  _Cmpss1Regs                     
0     00005ca0  _Cmpss2Regs                     
0     00005cc0  _Cmpss3Regs                     
0     00005ce0  _Cmpss4Regs                     
0     00005d00  _Cmpss5Regs                     
0     00005d20  _Cmpss6Regs                     
0     00005d40  _Cmpss7Regs                     
0     00005d60  _Cmpss8Regs                     
0     00005e00  _Sdfm1Regs                      
0     00005e80  _Sdfm2Regs                      
0     00006000  _McbspaRegs                     
0     00006040  _McbspbRegs                     
0     00006100  _SpiaRegs                       
0     00006110  _SpibRegs                       
0     00006120  _SpicRegs                       
0     00006130  _SpidRegs                       
0     00006340  _BgcrcCpuRegs                   
0     00006380  _BgcrcCla1Regs                  
0     00006400  _PmbusaRegs                     
0     00006600  _FsiTxaRegs                     
0     00006680  _FsiRxaRegs                     
0     00006700  _FsiTxbRegs                     
0     00006780  _FsiRxbRegs                     
0     00006880  _FsiRxcRegs                     
0     00006980  _FsiRxdRegs                     
0     00006a80  _FsiRxeRegs                     
0     00006b80  _FsiRxfRegs                     
0     00006c80  _FsiRxgRegs                     
0     00006d80  _FsiRxhRegs                     
0     00007000  _WdRegs                         
0     00007060  _NmiIntruptRegs                 
0     00007070  _XintRegs                       
0     00007200  _SciaRegs                       
0     00007210  _ScibRegs                       
0     00007220  _ScicRegs                       
0     00007230  _ScidRegs                       
0     00007300  _I2caRegs                       
0     00007340  _I2cbRegs                       
0     00007400  _AdcaRegs                       
0     00007480  _AdcbRegs                       
0     00007500  _AdccRegs                       
0     00007580  _AdcdRegs                       
0     00007900  _InputXbarRegs                  
0     00007920  _XbarRegs                       
0     00007940  _SyncSocRegs                    
0     00007980  _DmaClaSrcSelRegs               
0     00007a00  _EPwmXbarRegs                   
0     00007a80  _OutputXbarRegs                 
0     00007c00  _GpioCtrlRegs                   
0     00007f00  _GpioDataRegs                   
0     00008000  _RamfuncsLoadEnd                
0     00008000  _RamfuncsLoadStart              
0     00008000  _RamfuncsRunEnd                 
0     00008000  _RamfuncsRunStart               
0     0000a800  ___TI_enable_exit_profile_output
0     0000a802  ___TI_cleanup_ptr               
0     0000a804  ___TI_dtors_ptr                 
0     0000a806  __lock                          
0     0000a808  __unlock                        
0     00047000  _Emif1Regs                      
0     00047800  _Emif2Regs                      
0     00048000  _CanaRegs                       
0     0004a000  _CanbRegs                       
0     00057e00  _EcatssRegs                     
0     00057f00  _EcatssConfigRegs               
0     0005c400  _McanssRegs                     
0     0005c600  _McanRegs                       
0     0005c800  _McanErrorRegs                  
0     0005ce00  _Cpu1toCpu2IpcRegs              
0     0005ce40  _Cpu1toCmIpcRegs                
0     0005d000  _DevCfgRegs                     
0     0005d200  _ClkCfgRegs                     
0     0005d300  _CpuSysRegs                     
0     0005d400  _SysStatusRegs                  
0     0005d500  _SysPeriphAcRegs                
0     0005d700  _AnalogSubsysRegs               
0     0005dc00  _CmConfRegs                     
0     0005e000  _HwbistRegs                     
0     0005e700  _Dcc0Regs                       
0     0005e740  _Dcc1Regs                       
0     0005e780  _Dcc2Regs                       
0     0005e800  _EradGlobalRegs                 
0     0005e900  _EradHwbpRegs                   
0     0005e980  _EradCounterRegs                
0     0005ea00  _EradCrcRegs                    
0     0005f000  _DcsmZ1Regs                     
0     0005f080  _DcsmZ2Regs                     
0     0005f0c0  _DcsmCommonRegs                 
0     0005f400  _MemCfgRegs                     
0     0005f4c0  _Emif1ConfigRegs                
0     0005f4e0  _Emif2ConfigRegs                
0     0005f500  _AccessProtectionRegs           
0     0005f540  _MemoryErrorRegs                
0     0005f580  _RomWaitStateRegs               
0     0005f588  _RomPrefetchRegs                
0     0005f590  _TestErrorRegs                  
0     0005f800  _Flash0CtrlRegs                 
0     0005fb00  _Flash0EccRegs                  
0     00078000  _DcsmZ1Otp                      
0     00078200  _DcsmZ2Otp                      
0     00080000  code_start                      
0     00082000  _InitXbar                       
0     00082841  _InitGpio                       
0     00082bfa  _InitEPwm                       
0     00082d11  _InitSysCtrl                    
0     00082e08  _AdcSetMode                     
0     00082ebf  _InitAdca                       
0     00082f1e  _c_int00                        
0     00082f74  _CalAdcINL                      
0     00082fb1  C$$EXIT                         
0     00082fb1  _abort                          
0     00082fb3  _exit                           
0     00082fda  _copy_in                        
0     00082ffe  _InitPieVectTable               
0     00083020  _InitPieCtrl                    
0     0008303f  _main                           
0     0008305c  _memcpy                         
0     00083079  __args_main                     
0     0008308b  _EPWM1_ISR                      
0     0008309b  _CLA1CRC_INT_ISR                
0     000830a8  _CLB1_ISR                       
0     000830b5  _CLB2_ISR                       
0     000830c2  _CLB3_ISR                       
0     000830cf  _CLB4_ISR                       
0     000830dc  _CLB5_ISR                       
0     000830e9  _CLB6_ISR                       
0     000830f6  _CLB7_ISR                       
0     00083103  _CLB8_ISR                       
0     00083110  _CMTOCPUXIPC0_ISR               
0     0008311d  _CMTOCPUXIPC1_ISR               
0     0008312a  _CMTOCPUXIPC2_ISR               
0     00083137  _CMTOCPUXIPC3_ISR               
0     00083144  _CMTOCPUXIPC4_ISR               
0     00083151  _CMTOCPUXIPC5_ISR               
0     0008315e  _CMTOCPUXIPC6_ISR               
0     0008316b  _CMTOCPUXIPC7_ISR               
0     00083178  _CM_STATUS_ISR                  
0     00083185  _CPUCRC_INT_ISR                 
0     00083192  _ECATRSTINTN_ISR                
0     0008319f  _ECATSYNC0_ISR                  
0     000831ac  _ECATSYNC1_ISR                  
0     000831b9  _ECAT_ISR                       
0     000831c6  _EMPTY_ISR                      
0     000831d3  _EPWM13_ISR                     
0     000831e0  _EPWM13_TZ_ISR                  
0     000831ed  _EPWM14_ISR                     
0     000831fa  _EPWM14_TZ_ISR                  
0     00083207  _EPWM15_ISR                     
0     00083214  _EPWM15_TZ_ISR                  
0     00083221  _EPWM16_ISR                     
0     0008322e  _EPWM16_TZ_ISR                  
0     0008323b  _FMC_ISR                        
0     00083248  _FSIRXA1_ISR                    
0     00083255  _FSIRXA2_ISR                    
0     00083262  _FSIRXB1_ISR                    
0     0008326f  _FSIRXB2_ISR                    
0     0008327c  _FSIRXC1_ISR                    
0     00083289  _FSIRXC2_ISR                    
0     00083296  _FSIRXD1_ISR                    
0     000832a3  _FSIRXD2_ISR                    
0     000832b0  _FSIRXE1_ISR                    
0     000832bd  _FSIRXE2_ISR                    
0     000832ca  _FSIRXF1_ISR                    
0     000832d7  _FSIRXF2_ISR                    
0     000832e4  _FSIRXG1_ISR                    
0     000832f1  _FSIRXG2_ISR                    
0     000832fe  _FSIRXH1_ISR                    
0     0008330b  _FSIRXH2_ISR                    
0     00083318  _FSITXA1_ISR                    
0     00083325  _FSITXA2_ISR                    
0     00083332  _FSITXB1_ISR                    
0     0008333f  _FSITXB2_ISR                    
0     0008334c  _I2CA_HIGH_ISR                  
0     00083359  _MCANSS0_ISR                    
0     00083366  _MCANSS1_ISR                    
0     00083373  _MCANSS_ECC_CORR_PLS_ISR        
0     00083380  _MCANSS_WAKE_AND_TS_PLS_ISR     
0     0008338d  _PBIST_ISR                      
0     0008339a  _PMBUSA_ISR                     
0     000833a7  _PwmViennaOn                    
0     000833b4  _SDFM1DR1_ISR                   
0     000833c1  _SDFM1DR2_ISR                   
0     000833ce  _SDFM1DR3_ISR                   
0     000833db  _SDFM1DR4_ISR                   
0     000833e8  _SDFM2DR1_ISR                   
0     000833f5  _SDFM2DR2_ISR                   
0     00083402  _SDFM2DR3_ISR                   
0     0008340f  _SDFM2DR4_ISR                   
0     0008341c  _SPID_RX_ISR                    
0     00083429  _SPID_TX_ISR                    
0     00083436  _SYS_ERR_ISR                    
0     00083443  _InitWatchdog                   
0     0008344f  _ADCA1_ISR                      
0     00083459  _ADCA2_ISR                      
0     00083463  _ADCA3_ISR                      
0     0008346d  _ADCA4_ISR                      
0     00083477  _ADCA_EVT_ISR                   
0     00083481  _ADCB1_ISR                      
0     0008348b  _ADCB2_ISR                      
0     00083495  _ADCB3_ISR                      
0     0008349f  _ADCB4_ISR                      
0     000834a9  _ADCB_EVT_ISR                   
0     000834b3  _ADCC1_ISR                      
0     000834bd  _ADCC2_ISR                      
0     000834c7  _ADCC3_ISR                      
0     000834d1  _ADCC4_ISR                      
0     000834db  _ADCC_EVT_ISR                   
0     000834e5  _ADCD1_ISR                      
0     000834ef  _ADCD2_ISR                      
0     000834f9  _ADCD3_ISR                      
0     00083503  _ADCD4_ISR                      
0     0008350d  _ADCD_EVT_ISR                   
0     00083517  _CANA0_ISR                      
0     00083521  _CANA1_ISR                      
0     0008352b  _CANB0_ISR                      
0     00083535  _CANB1_ISR                      
0     0008353f  _CIPC0_ISR                      
0     00083549  _CIPC1_ISR                      
0     00083553  _CIPC2_ISR                      
0     0008355d  _CIPC3_ISR                      
0     00083567  _CLA1_1_ISR                     
0     00083571  _CLA1_2_ISR                     
0     0008357b  _CLA1_3_ISR                     
0     00083585  _CLA1_4_ISR                     
0     0008358f  _CLA1_5_ISR                     
0     00083599  _CLA1_6_ISR                     
0     000835a3  _CLA1_7_ISR                     
0     000835ad  _CLA1_8_ISR                     
0     000835b7  _CLA_OVERFLOW_ISR               
0     000835c1  _CLA_UNDERFLOW_ISR              
0     000835cb  _DATALOG_ISR                    
0     000835d5  _DMA_CH1_ISR                    
0     000835df  _DMA_CH2_ISR                    
0     000835e9  _DMA_CH3_ISR                    
0     000835f3  _DMA_CH4_ISR                    
0     000835fd  _DMA_CH5_ISR                    
0     00083607  _DMA_CH6_ISR                    
0     00083611  _ECAP1_ISR                      
0     0008361b  _ECAP2_ISR                      
0     00083625  _ECAP3_ISR                      
0     0008362f  _ECAP4_ISR                      
0     00083639  _ECAP5_ISR                      
0     00083643  _ECAP6_2_ISR                    
0     0008364d  _ECAP6_ISR                      
0     00083657  _ECAP7_2_ISR                    
0     00083661  _ECAP7_ISR                      
0     0008366b  _EMIF_ERROR_ISR                 
0     00083675  _EMU_ISR                        
0     0008367f  _EPWM10_ISR                     
0     00083689  _EPWM10_TZ_ISR                  
0     00083693  _EPWM11_ISR                     
0     0008369d  _EPWM11_TZ_ISR                  
0     000836a7  _EPWM12_ISR                     
0     000836b1  _EPWM12_TZ_ISR                  
0     000836bb  _EPWM1_TZ_ISR                   
0     000836c5  _EPWM2_ISR                      
0     000836cf  _EPWM2_TZ_ISR                   
0     000836d9  _EPWM3_ISR                      
0     000836e3  _EPWM3_TZ_ISR                   
0     000836ed  _EPWM4_ISR                      
0     000836f7  _EPWM4_TZ_ISR                   
0     00083701  _EPWM5_ISR                      
0     0008370b  _EPWM5_TZ_ISR                   
0     00083715  _EPWM6_ISR                      
0     0008371f  _EPWM6_TZ_ISR                   
0     00083729  _EPWM7_ISR                      
0     00083733  _EPWM7_TZ_ISR                   
0     0008373d  _EPWM8_ISR                      
0     00083747  _EPWM8_TZ_ISR                   
0     00083751  _EPWM9_ISR                      
0     0008375b  _EPWM9_TZ_ISR                   
0     00083765  _EQEP1_ISR                      
0     0008376f  _EQEP2_ISR                      
0     00083779  _EQEP3_ISR                      
0     00083783  _FPU_OFLOW_ISR                  
0     0008378d  _FPU_UFLOW_ISR                  
0     00083797  _I2CA_FIFO_ISR                  
0     000837a1  _I2CA_ISR                       
0     000837ab  _I2CB_FIFO_ISR                  
0     000837b5  _I2CB_ISR                       
0     000837bf  _ILLEGAL_ISR                    
0     000837c9  _MCBSPA_RX_ISR                  
0     000837d3  _MCBSPA_TX_ISR                  
0     000837dd  _MCBSPB_RX_ISR                  
0     000837e7  _MCBSPB_TX_ISR                  
0     000837f1  _NMI_ISR                        
0     000837fb  _NOTUSED_ISR                    
0     00083805  _PIE_RESERVED_ISR               
0     0008380f  _RTOS_ISR                       
0     00083819  _SCIA_RX_ISR                    
0     00083823  _SCIA_TX_ISR                    
0     0008382d  _SCIB_RX_ISR                    
0     00083837  _SCIB_TX_ISR                    
0     00083841  _SCIC_RX_ISR                    
0     0008384b  _SCIC_TX_ISR                    
0     00083855  _SCID_RX_ISR                    
0     0008385f  _SCID_TX_ISR                    
0     00083869  _SDFM1_ISR                      
0     00083873  _SDFM2_ISR                      
0     0008387d  _SPIA_RX_ISR                    
0     00083887  _SPIA_TX_ISR                    
0     00083891  _SPIB_RX_ISR                    
0     0008389b  _SPIB_TX_ISR                    
0     000838a5  _SPIC_RX_ISR                    
0     000838af  _SPIC_TX_ISR                    
0     000838b9  _TIMER0_ISR                     
0     000838c3  _TIMER1_ISR                     
0     000838cd  _TIMER2_ISR                     
0     000838d7  _USBA_ISR                       
0     000838e1  _USER10_ISR                     
0     000838eb  _USER11_ISR                     
0     000838f5  _USER12_ISR                     
0     000838ff  _USER1_ISR                      
0     00083909  _USER2_ISR                      
0     00083913  _USER3_ISR                      
0     0008391d  _USER4_ISR                      
0     00083927  _USER5_ISR                      
0     00083931  _USER6_ISR                      
0     0008393b  _USER7_ISR                      
0     00083945  _USER8_ISR                      
0     0008394f  _USER9_ISR                      
0     00083959  _WAKE_ISR                       
0     00083963  _XINT1_ISR                      
0     0008396d  _XINT2_ISR                      
0     00083977  _XINT3_ISR                      
0     00083981  _XINT4_ISR                      
0     0008398b  _XINT5_ISR                      
0     00083995  _EnableInterrupts               
0     0008399e  __register_unlock               
0     000839a2  __register_lock                 
0     000839a6  __nop                           
0     000839a7  _SetInterrupts                  
0     000839ae  __system_pre_init               
0     000839b0  __system_post_cinit             
0     00088000  ___cinit__                      
0     00088000  cinit                           
0     0008801c  _PieVectTableInit               
abs   00000000  _RamfuncsLoadSize               
abs   00000000  _RamfuncsRunSize                
abs   00000200  __STACK_SIZE                    
abs   ffffffff  .text                           
abs   ffffffff  ___TI_pprof_out_hndl            
abs   ffffffff  ___TI_prof_data_size            
abs   ffffffff  ___TI_prof_data_start           
abs   ffffffff  ___binit__                      
abs   ffffffff  ___c_args__                     
abs   ffffffff  ___etext__                      
abs   ffffffff  ___pinit__                      
abs   ffffffff  ___text__                       
abs   ffffffff  binit                           
abs   ffffffff  etext                           
abs   ffffffff  pinit                           

[398 symbols]

I still don't understand why 4/ doesn't work. I am not used to analyse the map file but I can see the EPWM1_ISR is in different location when I compare the 2 map files. Do you notice something wrong ?

Regards,

Adrien

Here we go !! As I wanted to have only relevant files and functions for my project, I had removed an essential part which is to copy from Flash location to RAM location. I added that copy, using the memcpy function as it's done in C2000Ware files and it's working perfectly.

You mean double checking with the .map file or using an other method ? (it changes at RAMLS0, 0x8000 in the .map file but it's not very explicit)

Interessant thing is to compare the latency when my ISR is executed from Flash which is 137ns (see case 5 above) and the latency when my ISR is executed from RAM. Now it's working, I measure 96ns. It saves a couple of clock pulses.

Last question: I see you use a function to initialize Flash and to setup flash waitstates. Do you advice to use the same setup ? For the moment, I don't do anything about Flash initialization in my application.

Thank you Veena, I have a much better understanding of how this works now.

Adrien

One important thing, if I want to run several ISR from RAM, do I need to create one section per ISR or one unique section can be ok for all ISRs ?

In other words, if the .TI.ramfunc contains several interrupts for example. When an interrupt is triggered, all functions located in the section are executed or only the ISR that is triggered is executed ?

Regards,

Adrien

HI Adrien,

ADRIEN CREUSVAUX said:

You mean double checking with the .map file or using an other method ? (it changes at RAMLS0, 0x8000 in the .map file but it's not very explicit)

I meant to check the address contents using the Disassembly or Memory Browser view while the device is connected via debugger.

ADRIEN CREUSVAUX said:

Last question: I see you use a function to initialize Flash and to setup flash waitstates. Do you advice to use the same setup ? For the moment, I don't do anything about Flash initialization in my application.

Since you are using Flash memory, you should be invoking Flashinit function. Waitstates are important especially after configuring the PLL when the system clock is higher

ADRIEN CREUSVAUX said:

One important thing, if I want to run several ISR from RAM, do I need to create one section per ISR or one unique section can be ok for all ISRs ?

You can put multiple ISR function in the ramfuncs sections. This just tells the linker to allocate a different Load address and Run address. Functionally there should be no difference, except the execution cycles. When an interrupt is triggered only the corresponding ISR is executed.

Regards,

Veena

It's clear, thanks for all the precious information.

Regards,

Adrien