• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 473 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28335: Use F28335 and FPGA to realize parallel CAN FIFO communication

Angela Zou
Intellectual 1055 points
Part Number: TMS320F28335


Hi experts,

My customer wants to use F28335 and FPGA to realize parallel CAN FIFO communication. How can we do? Do you any examples or demos? Thank you in advance!

  • 0
    TI__Guru* 95315 points

    Angela,

       No, we don't have any examples or demos. I don't quite understand how this is even possible. If you could explain further what exactly is the problem customer is attempting to solve, I may be able to help.

  • 0 in reply to Hareesh Janakiraman
    TI__Intellectual 1055 points

    Hi Hareesh,

    The CAN universal bus controller is implemented with FPGAs. They want to use XINTF to communicate between the FPGA and the F28335. They want us to confirm if the F28335 XINTF can fulfill their requirements: Timing, pins connection, etc.

    Here is their receive FIFO timing:

     

  • 0 in reply to Angela Zou
    TI__Guru* 95315 points

    Angela,

                    I am surprised that they don’t want to use the on-chip CAN module of the F28335 but would rather implement it using an external FPGA interfaced through the XINTF. Perhaps it would be far simpler to handle the FIFO function in software on the F28335, rather than deal with the complexity of interfacing the FPGA over the XINTF bus (and the associated software).

    Unfortunately, the timing diagram attached does not convey anything meaningful.

    Angela Zou said:
    They want us to confirm if the F28335 XINTF can fulfill their requirements:

    XINTF timing information is available in the datasheet. As to whether their FPGA will work with the XINTF, they need to look into the timing requirement of the FPGA and determine whether it would work with the XINT. We would not be able to help them with that.