Hi TI
where I can find related documentation about ADCCLK setting and ACQ setting.
I guess the timing setting should related to silicon design in the chip.
and from the datasseht I found there are additional manual for specific chip.
so where I can find that.
thanks
Hi Dragon,
Are you trying to find out the relationship of ADCLK and ACQ (sampling and hold) settings? ADCLK and ACQ settings are independent of each other.
- ADCLK setting determines how long for the ADC to convert the analog signal into digital values being available in the ADC Results register. ADCCLK is derived from SYSCLK and prescaler is set in register ADCCTL2 (see TRM for details). You should not exceed 50Mhz clock for ADCCLK (refer to datasheet sections 7.11.2.3.x ADC Operating Conditions for ADCCLK in both 12 and 16-bit modes)
- ACQPS setting determines how long the sampling capacitor in the ADC SAR block will close to sample the input analog signal. This is expressed in terms of # of SYSCLK and set in ADCSOCxCTL registers (see TRM for details). ACQPS (S/H) is set based on the input impedance of the signal source as seen by the analog input pin. The signal source, along with the analog input model (fig 7-31 and 7-32 in the datasheet) would form a complex RC filter that would resemble low pass filters and this means that the sample and hold times have to account for these impedances in order to have the optimum setting for signal sampling. A thorough discussion and example of determination of sampling time is discussed in 20.13 Choosing an Acquisition Window Duration in the TRM.
The overall throughput of the ADC will be determined by ADCLK and ACQPS settings and this is illustrated in the ADC Timings section of both the datasheet and TRM through tables and timing diagrams, like below:
Additionally, you can also look at below application notes to assist in input signal conditioning circuits to get the best performance of the ADC:
Regards,
Joseph
