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Original question:
I'm trying to think of a way to solve the missing bit problem in IDDK2.2 Tamagawa Encodr reciving data by enabling reception just before the data is sent, and setting the SPI length to 10 bits.
So, to control the SPISTE signal, I'm going to output CLB4_OUT0 to GPIO6 port to control SPISTE.
I have configured the port settings as follows
In GPIO config
//GPIO6 XBAROUT
GPIO_setMasterCore(6, GPIO_CORE_CPU1);
GPIO_setPinConfig(GPIO_6_OUTPUTXBAR4); // out x bar for spiste
In Xbar Setting
XBAR_setOutputMuxConfig(OUTPUTXBAR_BASE, XBAR_OUTPUT4,
XBAR_OUT_MUX24_CLB4_OUT0);
XBAR_enableOutputMux(OUTPUTXBAR_BASE, XBAR_OUTPUT4, XBAR_MUX24);
I tried to see if I could get some kind of signal out of it by doing the same thing with the TXen signal and putting the same formula for FSM2_OUT in the TILE_OUT0 signal as in TILE_OUT4 to see if I could get the same signal as TXen, but nothing came out.
What am I doing wrong with this?
Please let me know how to solve this.
Hello, I am looking into this. To confirm, I think you are using the F28388x devices (not F2837x) is that correct?
If so, each of the CLB_OUTPUTXBARs is connected to specific IO pins. For example, CLB_OUTPUTXBAR2 can be connected to GPIO33 using the driverlib function:
This information is found in the GPIO Muxed Pins table of the Technical Reference Manual (TRM) and in the Pin Attributes table of the datasheet.
You may also find SysConfig useful. It will show you in the pulldown which I/O can be used with which CLB_OUTPUTXBAR and generate the code to do so.
Here is more information about the tool:
Regards
Lori
