TMS320F28377D: System clock change when resetting the WDHALTI bit.

S Tarik,

We are forwarding your query to the expert. Please expect response in a day.

Best Regards

Siddharth

Hi S.Tarik,

I am unable to reproduce the issue. How are you setting the bit? Can you share the code snippet?

Is the application entering HALT mode?

Regards,

Veena

Hello Veena,

How I could verify that the application is entering the HALt mode?

you could take a loot to your private message, please?

Hi,

The HALT mode is entered by configuring the LPMCR register and executing the IDLE instruction.

There is known issue, documented in the Errata document that "Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang". Not sure if this is causing the issue. From the code you shared, I see back to back writes to CLKSRCCTL1. Can you try after inserting the required delay?

Regards,

Veena

Hi,

I added 300 cycles for each time I write to the CLKSRCCTL1 but still have the same issue.

S.T

I tried a C2000ware example and added a code that sets and resets the WDHALTI bit. I was unable to see the issue.

To make sure it is not a hardware issue, can you try out the same?

- Import any example from <C2000ware>\device_support\f2837xd\examples\cpu1

- InitSysCtrl() function configures the PLL and other clock settings.

- Add your code snippet that writes to the WDHALTI bit and check if the multipliers are reset?

Regards,

Veena

Hello Veena,

I noticed that in our project, we are executing the same code in the boot for cpu1 and cpu2 and we check that in the APP/BSP.

if the configuration is done,  this "ClkCfgRegs.CLKSRCCTL1.bit.WDHALTI = 0; "line is executed many times (2 times) for cpu1 and (2 times)  cpu2.

I suggest an update of the current driver and the configuration for the clock must be done just using the master cpu1 in the boot and we check in APP/BSP using cpu1. Cpu2 is not responsible for this system clock finally, do you recommend this architecture?

we want also to be able to use the WD for the two CPUs.

Regards,