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F2812 Interrupt Freeze

Josh Warr
Intellectual 410 points

I have an F2812 with an external chip connected to INT13.  Occasionally the F2812 gets into a state where INT13 is asserted, but the corresponding bit in the IFR register (bit 12) is not set.  I have verified that when the CPU is in this state, bit 12 in IER is high, and interrupts are globally enabled.  But all indications are that my ISR was never called.  If I stop the CPU via CC Studio and manually write a 1 to bit 12 of IFR, and the ISR is called.  

Is the F2812 edge or level sensitive to interrupts?  The F2812 documentation that I have searched seems to indicate that interrupts are level sensitive.  However, if they are level sensitive, I do not know how the CPU could get into the state that I am seeing.

Any insight into this issue will be much appreciated.

Thanks

--Josh Warr

  • 0
    Genius 5885 points

    Hi Josh,

    F2812 CPU (note the CPU) is level sensitive to interrupts. The XNMI logic generates appropriate signal based on the edge of the XNMI signal. Beware that the signal for XNMI logic goes through GPIO input qualification which might be set up so that it rejects very short pulses. Also check the errata for GPIO input qualification as with some C2000 CPUs there are some issues with this part.

    Regards, Mitja

  • 0 in reply to Mitja Nemec
    Intellectual 410 points

    Thanks for the explanation.  Right, the interrupt logic is edge triggered.  That is what I didn't understand.

    I discovered that my problem was occurring because the external device was not getting acknowledge due to memory being trashed.  Since the interrupt wasn't acknowledged, there was never another edge into the interrupt logic.  So even though the external device was asserting the interrupt, the interrupt logic never saw another interrupt, and the ISR was never called again.