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TMS320F28377D: PLL clock verification using timers.

UserHomeInit
Expert 2205 points
Part Number: TMS320F28377D


Dear TI hello,

In the F2837xD_SysCtrl.c TI uses timers to calculate the error clock.

Could you clarify please why we are using these macros to load timers:

#define TMR1SYSCLKCTR        0xF0000000
#define TMR2INPCLKCTR        0x800

Could you explain please the part when the timers are used for this purpose?

Thank you  in advance,

S.Tarik

  • 0
    TI__Guru* 95315 points

    Tariq,

                    Please refer to the Advisory PLL: May Not Lock on the First Lock Attempt in page 21 of www.ti.com/lit/SPRZ412.

  • 0 in reply to Hareesh Janakiraman
    Expert 2205 points

    Hareesh,

    Yes, I have seen this, but the question about the timers used in the PLL configuration.

    I could understand how the timer could help us measure the error, could help me with that please?

    Could you clarify please why we are using these macros to load timers

    #define TMR1SYSCLKCTR 0xF0000000
    #define TMR2INPCLKCTR 0x800

     CpuTimer2Regs.TCR.bit.TIF = 1;                                    // clear interrupt flag
        CpuTimer2Regs.TCR.bit.TIE = 1;                                    // enable interrupt
        CpuTimer2Regs.TCR.bit.TSS = 1;                                    // stop timer2
        CpuTimer2Regs.PRD.all = TMR2INPCLKCTR;                            // seed timer2 counter
        CpuTimer2Regs.TPR.bit.TDDR = 0x0;                                 // sysclock divider
        CpuTimer2Regs.TCR.bit.TRB = 1;                                    // reload timer with value in PRD

        //
        // Stop/Start timer counters
        //
        CpuTimer1Regs.TCR.bit.TSS = 1;                                    // stop timer1
        CpuTimer2Regs.TCR.bit.TSS = 1;                                    // stop timer2
        CpuTimer1Regs.TCR.bit.TRB = 1;                                    // reload timer1 with value in PRD
        CpuTimer2Regs.TCR.bit.TRB = 1;                                    // reload timer2 with value in PRD
        CpuTimer2Regs.TCR.bit.TIF = 1;                                    // clear timer2 interrupt flag
        CpuTimer2Regs.TCR.bit.TSS = 0;                                    // start timer2
        CpuTimer1Regs.TCR.bit.TSS = 0;                                    // start timer1

        //
        // Stop timers if either timer1 or timer2 counters overflow
        //
        while((CpuTimer2Regs.TCR.bit.TIF == 0) && (CpuTimer1Regs.TCR.bit.TIF == 0));

        CpuTimer1Regs.TCR.bit.TSS = 1;                                    // stop timer1
        CpuTimer2Regs.TCR.bit.TSS = 1;                                    // stop timer2

        //
        // Calculate elapsed counts on timer1
        //
        ctr1 = TMR1SYSCLKCTR - CpuTimer1Regs.TIM.all;

        //
        // Restore timer settings
        //
        CpuTimer1Regs.TCR.all = t1TCR;
        CpuTimer1Regs.PRD.all = t1PRD;
        CpuTimer1Regs.TPR.all = t1TPR;
        CpuTimer1Regs.TPRH.all = t1TPRH;
        CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC;
        CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale;
        CpuTimer2Regs.TCR.all = t2TCR;
        CpuTimer2Regs.PRD.all = t2PRD;
        CpuTimer2Regs.TPR.all = t2TPR;
        CpuTimer2Regs.TPRH.all = t2TPRH;

        //
        // Calculate Clock Error:
        // Error = (mult/div) - (timer1 count/timer2 count)
        //
        mult = (float)(imult) + (float)(fmult)/4;
        div = (float)((!ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV) ? 1 : (ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV << 1));

        sysclkToInClkError = (mult/div) - ((float)ctr1/(float)TMR2INPCLKCTR);

    Regards,

    S.Tarik

  • +1 in reply to UserHomeInit
    TI__Genius 15385 points

    Hey Tarik,

    Timers are used to measure the PLLCLK frequency.

    Timer1 runs on SYSCLK (i.e. PLLCLK), this is set to max/high value of 0xF0000000 and it counts down once timer enables. Timer2 runs on OSCCLK which is a reference clock, this defines the window of measurement, so it is set to lower value i.e. 0x800.

    When Timer2 counter overflows, ratio of Timer1 counts (i.e. 0xF0000000-measured counts) and Timer2 counts (i.e. 0x800) is computed, which should be same as imult value (PLLCLK = OSCCLK*imult).

    Best Regards,

    Nirav