• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 82 subscribers
  • Views 402 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280049: The ADC pin is pulled low internally

Cherry Zhou
Mastermind 22235 points

Part Number: TMS320F280049

Hi team,

Here's an issue from the customer may need your help:

The operational discharge output voltage of the sampling circuit is 1.47 V, connected to the ADC port with a 220 ohm resistor. But the level dropped to 0.7 V.

The ADC sampling ports for the same function are abnormal, characterized by the fact that the three AD samples are configured as inputs to the CMPSS module and that the other unset ADC sampling ports are working properly. Why the configuration will have such impact?

Could you help check this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Mastermind 44340 points

    Hi Cherry,

    Is the attenuation happening on any ADC input or is it just certain channels?  Can you share the ADC channel/CMPSS setup code?

    Thanks,

    Joseph

  • 0 in reply to Joseph Casuga
    TI__Mastermind 22235 points

    Hi Joseph,

    Thanks for your help.

    Joseph Casuga said:
    or is it just certain channels?

    It only happened 3 ADC channels configured for CMPSS.

    void ADC_Init(void)
{
SetVREF(ADC_ADCA, ADC_EXTERNAL, ADC_VREF3P3);
SetVREF(ADC_ADCC, ADC_EXTERNAL, ADC_VREF3P3);
EALLOW;
// Set ADCCLK divider to /4
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //100M/4=25M
AdccRegs.ADCCTL2.bit.PRESCALE = 6; //100M/4=25M
// Set pulse positions to late
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
// Power up the ADC and then delay for 1 ms
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
EDIS;
DELAY_US(1000);
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 2; // SOC0 will convert pin A2---配置了CMPSS
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 0; // Trigger on software
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 4; // SOC1 will convert pin A4---配置了CMPSS
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 0; // Trigger on software
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 6; // SOC2 will convert pin A6---配置了CMPSS
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 0; // Trigger on software
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 2; // End of SOC2 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared
//
AdccRegs.ADCSOC0CTL.bit.CHSEL = 0; // SOC0 will convert pin C0
AdccRegs.ADCSOC0CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 0; // Trigger on software
AdccRegs.ADCSOC1CTL.bit.CHSEL = 1; // SOC1will convert pin C1
AdccRegs.ADCSOC1CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 0; // Trigger on software
AdccRegs.ADCSOC2CTL.bit.CHSEL = 2; // SOC2 will convert pin C2
AdccRegs.ADCSOC2CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdccRegs.ADCSOC2CTL.bit.TRIGSEL = 0; // Trigger on software
AdccRegs.ADCSOC3CTL.bit.CHSEL = 6; // SOC3 will convert pin C6
AdccRegs.ADCSOC3CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdccRegs.ADCSOC3CTL.bit.TRIGSEL = 0; // Trigger on software
AdccRegs.ADCSOC4CTL.bit.CHSEL = 8; // SOC4 will convert pin C8
AdccRegs.ADCSOC4CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdccRegs.ADCSOC4CTL.bit.TRIGSEL = 0; // Trigger on software
AdccRegs.ADCSOC5CTL.bit.CHSEL = 10; // SOC5 will convert pin C10
AdccRegs.ADCSOC5CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdccRegs.ADCSOC5CTL.bit.TRIGSEL = 0; // Trigger on software
AdccRegs.ADCSOC6CTL.bit.CHSEL = 14; // SOC6 will convert pin C14
AdccRegs.ADCSOC6CTL.bit.ACQPS = 4; // Sample window is 10 SYSCLK cycles
AdccRegs.ADCSOC6CTL.bit.TRIGSEL = 0; // Trigger on software
AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 6; // End of SOC6 will set INT1 flag
AdccRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared
EDIS;
}

    Thanks and regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Mastermind 44340 points

    Hi Cherry,

    Thanks for sending the code.  There is nothing obvious in the ADC channels/CMPSS mux combinations and setup that causes the signal attenuation.  Are there any other components on the PFCA-InCurr-SENSE node going to the F280049 device or does it go directly to the analog channels?  Is it possible to see the schematics on the analog input side of the F280049?

    Best regards,

    Joseph