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TMS320F280039C: Power sequence confirmation

Songzhen Guo
Intellectual 2840 points

Part Number: TMS320F280039C

Hi Experts,

F290039C is under evaluation on customer side. They are working on the schematic now.

Based on the datasheet of F280039C, there are two parameters need to confirm:

1. For external VREG Power Up sequence, VDDIO should come up first, ad VDD should come up next; 

Could you confirm the most suitable delay for those two power? It just show the min value, how about the max value?

2. For the power up SR, VDDIO and VDD need meet 20~100mV/us. It show the faster SR will trigger internal ESD. Could you share the detail information for this? 

Otherwise, if the power up SR too slow(< 20mV/us), what's the effect on device?

Best Regards

Songzhen Guo

  • 0
    TI__Mastermind 28275 points

    Hi Songzhen,

    Songzhen Guo said:

    1. For external VREG Power Up sequence, VDDIO should come up first, ad VDD should come up next; 

    Could you confirm the most suitable delay for those two power? It just show the min value, how about the max value?

    There is no max value which is why the max is blank. The only restriction is that VDD cannot come up before VDDIO which is what the min value of "0" is indicating.

    Songzhen Guo said:
    2. For the power up SR, VDDIO and VDD need meet 20~100mV/us. It show the faster SR will trigger internal ESD. Could you share the detail information for this? 

    Yes, faster ramps than 100mV/us can trigger the ESD structures. This is intentional because the ESD structures are intended to protect the device from electrostatic discharge voltage spikes which tend to be very fast rising spikes.

    Songzhen Guo said:
    Otherwise, if the power up SR too slow(< 20mV/us), what's the effect on device?

    This is explained in the "6.12.1.4.3.4 Supply Slew Rate" section.

    Let us know if you have more questions or any of the above is unclear.

  • 0 in reply to Frank Ankapong
    TI__Intellectual 2840 points

    Hi Frank,

    Thanks for your feedback.

    I also want to the testing method for this slew rate, could you share the power slew rate waveform of VDDIO and VDD?

    So I can let customer to follow the testing method from us. Thanks.

    Best Regards

    Songzhen Guo

  • 0 in reply to Songzhen Guo
    TI__Mastermind 28275 points

    Hi Songzhen,

    We use programmable bench supplies to generate different ramps. I wasn't clear on your question, what kind of testing is the customer looking to do here?