Other Parts Discussed in Thread: SYSCONFIG, C2000WARE
Dear team:
My client wants to modify the routine(spi_ex1_loopback.c) to the communication between two F280049C chips. (the routine has been able to communicate normally)
The customer has divided the program in the internal loopback mode into master program and slave program, enabling FIFO and its interrupt respectively, but the correct transmission waveform is not observed after connecting the corresponding pin.
He mainly modified the following two codes:
SpiaRegs.SPICCR.bit.SPILBK = 0;
...
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
What changes need to be made?
#include "F28x_Project.h"
interrupt void spiTxFifoIsr(void);
interrupt void spiRxFifoIsr(void);
void delay_loop(void);
void initSPIFIFO(void);
void InitSpi(void);
void error(void);
Uint16 sdata[8]; // Send data buffer
Uint16 rdata[8]; // Receive data buffer
Uint16 errcounter;
Uint16 rdata_point; // Keep track of where we are
// in the data stream to check received data
int m=0,n=0;
void main(void)
{
Uint16 i;
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
InitSpiaGpio();
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.SPIA_RX_INT = &spiRxFifoIsr;
PieVectTable.SPIA_TX_INT = &spiTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers
initSPIFIFO();
for(i=0;i<8;i++)
{
sdata[i]=i;
}
rdata_point = 0;
errcounter=0;
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER6.bit.INTx1=1; // Enable PIE Group 6, INT 1
PieCtrlRegs.PIEIER6.bit.INTx2=1; // Enable PIE Group 6, INT 2
IER=0x20;
// IER = M_INT6// Enable CPU INT6
EINT;
// sdata = 0;
for(;;);
}
void error(void)
{
errcounter++;
asm(" ESTOP0"); // Test failed!! Stop!
for(;;);
}
void delay_loop()
{
long i;
for (i = 0; i < 10; i++) {}
}
void initSPIFIFO(void)
{
SpiaRegs.SPIFFTX.all =0xC028;
SpiaRegs.SPIFFRX.all = 0x0028;
SpiaRegs.SPIFFCT.all =0x00;
SpiaRegs.SPIFFTX.bit.TXFIFO=1;
SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;
// SpiaRegs.SPICCR.bit.SPISWRESET =0;
// SpiaRegs.SPICCR.all =0x001F;
// SpiaRegs.SPICTL.all =0x0017;
// SpiaRegs.SPISTS.all =0x0000;
// SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR;
// SpiaRegs.SPIFFTX.all =0xC028;
// SpiaRegs.SPIFFRX.all =0x0028;
// SpiaRegs.SPIFFCT.all =0x00;
// SpiaRegs.SPIPRI.all =0x0010;
// SpiaRegs.SPICCR.bit.SPISWRESET =1;
// SpiaRegs.SPIFFTX.bit.TXFIFO =1;
// SpiaRegs.SPIFFRX.bit.RXFIFORESET =1;
InitSpi();
}
void InitSpi(void)
{
// Set reset low before configuration changes
// Clock polarity (0 == rising, 1 == falling)
// 16-bit character
// Enable loop-back(1:使能回环 0:禁用回环)
//
SpiaRegs.SPICCR.bit.SPISWRESET = 0;
SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
SpiaRegs.SPICCR.bit.SPICHAR = (16-1);
SpiaRegs.SPICCR.bit.SPILBK = 1;
//
// Enable master (0 == slave, 1 == master)
// Enable transmission (Talk)
// Clock phase (0 == normal, 1 == delayed)
// SPI interrupts are disabled
//
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
SpiaRegs.SPICTL.bit.TALK = 1;
SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
SpiaRegs.SPICTL.bit.SPIINTENA = 0;
// Set the baud rate
//
// SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR;
SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 0x007F;
// Set FREE bit
// Halting on a breakpoint will not halt the SPI
SpiaRegs.SPIPRI.bit.FREE = 1;
//
// Release the SPI from reset
SpiaRegs.SPICCR.bit.SPISWRESET = 1;
}
/******发送中断配置*******/
interrupt void spiTxFifoIsr(void)
{
m++;
Uint16 i;
for(i=0;i<8;i++)
{
SpiaRegs.SPITXBUF =sdata[i];
}
for(i=0;i<8;i++) // Increment data for next cycle
{
sdata[i]++;
}
SpiaRegs.SPIFFTX.bit.TXFFINTCLR =1;
PieCtrlRegs.PIEACK.all|=0x20; // Issue PIE ACK
}
/*****接收中断配置********/
interrupt void spiRxFifoIsr(void)
{
n++;
Uint16 i;
for(i=0;i<8;i++)
{
rdata[i]=SpiaRegs.SPIRXBUF;
}
for(i=0;i<8;i++)
{
if(rdata[i]!=rdata_point+i)
{ error();}
}
rdata_point++;
SpiaRegs.SPIFFRX.bit.RXFFOVFCLR =1;
SpiaRegs.SPIFFRX.bit.RXFFINTCLR =1;
PieCtrlRegs.PIEACK.all|=0x20; // Issue PIE ACK
}