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TMS320F28384S: The noise immunity of SDFM

Luke Chen
Expert 5090 points
Part Number: TMS320F28384S


Hi champ,

In F2837x devices we suggest customers use SDFM I/O 3-sample for noise immunity, however we recommend using SDFM internal input qualification in F2838x devices along with SDFM I/O ASYNC setting.

Speaking of noise immunity capability, which method is better? Do we have analysis data to compare the noise immunity capabilities between F2837x and F2838x devices?

If customers use F2838x SDFM internal input qualification and don't get good noise immunity result, do we have any other settings to enhance SDFM noise immunity capability?

Regards,

Luke

  • 0
    TI__Mastermind 29461 points

    Luke,

    Luke Chen said:
    Speaking of noise immunity capability, which method is better? Do we have analysis data to compare the noise immunity capabilities between F2837x and F2838x devices?

    Let me look into this some more & see if there is any data we can share.

    Luke Chen said:
    If customers use F2838x SDFM internal input qualification and don't get good noise immunity result, do we have any other settings to enhance SDFM noise immunity capability?

    PCB design will be critical to getting clean SDFM signals.

  • 0 in reply to Gus Martinez
    TI__Expert 5090 points

    Gus,

    I understand the PCB design is very important for SDFM.

    I would like to double check is there any other register settings to enhance F2838x SDFM noise immunity capability, besides SDFM internal input qualification?

    Regards,

    Luke

  • 0 in reply to Luke Chen
    TI__Mastermind 29461 points

    Luke, none that I am aware of.

  • 0 in reply to Gus Martinez
    TI__Expert 5090 points

    Gus,

    I see. Please check if we have analysis data showing the performance difference between F2837x(3-sample) and F2838x(input QUAL.).

    Thanks and regards,

    Luke

  • 0 in reply to Luke Chen
    TI__Guru 55700 points

    Luke,

    In F2838x, GPIO QUAL option is not available to improve noise immunity. It is mandated to use SDFM internal input qualification. 

    All our simulations and timing closure was done only for SDFM internal input qualification and not for GPIO QUAL option. If customer choses GPIO QUAL option they will be violating datasheet timing requirements.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Expert 5090 points

    Manoj,

    I know this, we had several discussions in the past and thanks for your support.

    My customer is wondering which method is better for SDFM noise immunity, is it 3-sample on F2837x or SDFM  input qualification on F2838x?

    If customer uses SDFM input qualification in F2838x and gets not good enough noise immunity capability, is there any other settings he can try, besides review schematic/PCB?

    Regards,

    Luke

  • +1 in reply to Luke Chen
    TI__Guru 55700 points
    Luke Chen said:
    If customer uses SDFM input qualification in F2838x and gets not good enough noise immunity capability, is there any other settings he can try, besides review schematic/PCB?

    Is customer concerned about any particular noise profile? SDFM input qualification in F2838x performance was similar to GPIO QUAL option in F2837xD.

    We don't have any other setting which would provide additional noise immunity. But, in F2838x, we have clock control feature which allows you to share SD-C1 clock trace to source SD-C2 / C3 / C4. This reduces the number of high speed trace in PCB thereby reducing the chances of picking noise on SDFM pins.

  • 0 in reply to Manoj Santha Mohan
    TI__Expert 5090 points

    Manoj,

    SDFM input qualification in F2838x is similar to GPIO SYNC option in F2837x(but F2837x can use only GPIO 3-sample), is it correct?

    If customer shares SD-C1 clock to source SD-C2 / C3 / C4, should he sets SDCTLPARM1.SDCLKSEL bit to 1 or 0?

    When he uses SDFM internal input qualification, should he enable or disable SDFM GPIO internal pull-up in register GPAPUD?

    Thanks and regards,

    Luke

  • +1 in reply to Luke Chen
    TI__Guru 55700 points
    Luke Chen said:
    SDFM input qualification in F2838x is similar to GPIO SYNC option in F2837x(but F2837x can use only GPIO 3-sample), is it correct?

    Your understanding is correct!

    Luke Chen said:
    If customer shares SD-C1 clock to source SD-C2 / C3 / C4, should he sets SDCTLPARM1.SDCLKSEL bit to 1 or 0?

    It should be set to 0

    Luke Chen said:
    When he uses SDFM internal input qualification, should he enable or disable SDFM GPIO internal pull-up in register GPAPUD?

    It shouldn't matter whether you enable / disable pull-up

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Expert 5090 points

    Manoj,

    According to my customer's evaluation, it seems that there has no performance difference when he sets SDCTLPARM1.SDCLKSEL bit to 1 or 0.

    Does it mean actually SD-C1 connects to SD-C1 input pin no matter SDCTLPARM1.SDCLKSEL bit is 1 or 0?

    Regards,

    Luke

  • +1 in reply to Luke Chen
    TI__Guru 55700 points

    Yes. There is no difference when you choose 0 or 1 for CH1