TMS320F28388D: IPC communication control register exception

Green Deng

Dear team:

My customer tested the dual core communication of f28388d chip and used the internal IPC bus for transmission. Occasionally, the flag bit of the control register failed to respond.

CPU1 uses the SendIpcCommand function to notify CPU2 to transmit data. At the same time, CPU1 waits for CPU2 to respond to the result through WaitForIpcAck. After data processing, CPU2 responds through the SendIpcCommandAck function.

However, CPU1 will occasionally enter the dead cycle during debugging. while ((IpcRegs.IPCFLG.all & (1UL << flag)) != 0x00000000) {;}

Use the emulator to check the "IPCFLG" register(IPC remote flag status register) of CPU1. Only by manually resetting the IPCACK bit in CPU2, can the program push out the dead cycle and continue to execute.

What causes it?

Best regards

over 3 years ago

0 Manoj Santha Mohan over 3 years ago

TI__Guru 55700 points

Can you send me the code snippet which causes the issues? Feel free to attach code if necessary.

0 yu cao over 3 years ago in reply to Manoj Santha Mohan

Prodigy 20 points

1、Use IPC_sendCommand to send commands in CPU1, and then wait for CPU2 to reply ACK

2、CPU2 responds to CPU1

0 Manoj Santha Mohan over 3 years ago in reply to yu cao

TI__Guru 55700 points

IPC30 cannot generate CPU interrupt on either CPU1 / CPU2. For IPCs which cannot generate CPU interrupt, it is possible that CPU2 send ACK signal before CPU1 expects it (as both CPUs are not synchronized) and hence stuck in infinite loop. In such instances, you need to use synchronize both CPUs using IPC_sync(IPC_Type_t ipcType, uint32_t flag) function available in IPC.h before you use IPC30.

0 yu cao over 3 years ago in reply to Manoj Santha Mohan

Prodigy 20 points

In fact, we have used IPC_sync (IPC_Type_t ipcType, uint32_t flag) to synchronize the two CPUs when the program is initialized, and if we synchronize before each SendIpcCommand() command, it will greatly reduce the efficiency of the program execution, but we will try to test it like this to see the effect and efficiency of the final execution，tks ！

+1 Manoj Santha Mohan over 3 years ago in reply to yu cao

TI__Guru 55700 points

If you use IPC flags which don't generate CPU interrupt, it is important to synchronize the cores achieve predictable behavior,

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TMS320F28388D: IPC communication control register exception