Part Number: TMS320F28388D
Hi experts,
We applied EMIF1(32-bit mode, async-mode) to read & write access to FPGA.
We implement below functions to a bit to enable one function on FPGA.
typedef struct{
....
union{ /* FSCOM0_CONTROL_UN */
UINT32 Word_u32; /* UINT32 Access */
struct{ /* Bit Access */
UINT32 COM_EN : 1; /* BIT0 */
UINT32 ERROUT_EN : 1; /* BIT1 */
UINT32 Reserved : 7;
UINT32 ERROR_EXTERNAL : 1; /* BIT9 */
UINT32 ERROR_HSCOM : 1; /* BIT10 */
UINT32 ERROR_INTERNAL : 1; /* BIT11 */
UINT32 Reserved2 : 20;
}BIT_ST;
}FSCOM0_CONTROL_UN;
.....
}AX7_FSCOM0_ST;
volatile AX7_FSCOM0_ST AX7_fscom0_stg;
void AX7_Com0SetUnitEnable( void ){
AX7_fscom0_stg.FSCOM0_CONTROL_UN.BIT_ST.COM_EN = 1UL;
}
void AX7_Com0SetUnitEnable2( void ){
AX7_fscom0_stg.FSCOM0_CONTROL_UN.Word_u32 = 0x1UL;
}
However AX7_Com0SetUnitEnable() does not work correctly.
(AX7_Com0SetUnitEnable2() works fine).
And we disassemble those functions and put below.
TEXT Section .text:AX7_Com0SetUnitEnable (Little Endian), 0x6 words at 0x00000000 00000000 AX7_Com0SetUnitEnable: 00000000 0201 MOVB ACC, #1 00000001 761f MOVW DP, #0x1e 00000002 001e 00000003 9802 OR @0x2, AL 00000004 9903 OR @0x3, AH 00000005 0006 LRETR TEXT Section .text:AX7_Com0SetUnitEnable2 (Little Endian), 0x5 words at 0x00000000 00000000 AX7_Com0SetUnitEnable2: 00000000 0201 MOVB ACC, #1 00000001 761f MOVW DP, #0x1e 00000002 001e 00000003 1e02 MOVL @0x2, ACC 00000004 0006 LRETR
AX7_Com0SetUnitEnable() accesses with 16-bit twice (even and odd address)
and AX7_Com0SetUnitEnable2() accesses with 32-bit (even address).
CGT=ti-cgt-c2000_21.6.0.LTS
We do not find a compiler option to restrict r/w access with 32-bit for EMIF1 region.
And I do not know why CGT generates 16-bit access code in this case.
Could you please let us know how to treat this case ?
Best regards,
Hidehiko
