TMS320F280025: ADC sampling fequency

Hi Mohana,

Please refer to "ADC Timing Diagrams" section of the datasheet or TRM.

     1.) Determine SH (sample and hold) time.  This is (ACQPS+1)*(1/SYSCLK).

     2.) From the "ADC Timings" table, note ADC prescale used in ADCCTL2 and determine corresponding t_LAT from the list in SYSCLK cycles. For instance, if SYSCLK is 100MHz and ADC prescale used is 2, which means ADC CLK will set set at 100MHz/2, or 50MHz, then t_LAT will be 23 SYSCLK cycles from the table.  Conversion and latency time will be t_LAT*(1/SYSCLK)

     3.) Total conversion time will be SH + t_LAT*(1/SYSCLK).  Sampling frequency will be the reciprocal of total conversion time.

Regards,

Joseph