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TMS320F280049: F280049 High-frequency control period adc, pwm application, floating-point operation issues

Cherry Zhou
Mastermind 22235 points

Part Number: TMS320F280049

Hi team,

Here're few questions from the customer may need your help:

Using the F280049 as a digital power supply for a 500-kHz switching frequency, an interrupt is generated for three PWM cycles and an adc sample is triggered in the interrupt. When the end of the adc sample is detected, perform the PID algorithm, re-adjust the value of the CMPA, and then clear the interrupt flag bit.

1) since the result of multiple adc is required, if the acquisition is placed in the EPWM interrupt, there will be a long delay, resulting in the entire interrupt time well beyond 3 PWM cycles. Is there any other way to sample the ADC?

2) can CLA be used to reduce the time of the operation because there are many floating-point operations when processing the sampled data?

3) If CLA can be used, then sample + process data + update CMPAs, how should these be set?

4) Set up EPWM1 to generate both ADC SOC trigger signal and EPWM interrupt, ADC trigger first or EPWM interrupt first?

5) Does ADC sampling and conversion take up CPU time? 

6) The EPWM trigger SOC sampling and conversion should not be interrupts, and is the adc and interrupt parallel if the adc sampling and conversion do not take CPU time at this time? If the adc sampling and interrupts take CPU time, how to understand the order in which the adc conversion and EPWM interrupts are executed?

Could you help check this case? Thanks.

Best Regards,

Cherry

  • +1
    TI__Guru 52220 points

    Cherry,

    I will answer these to the best of my knowledge and then loop in the ADC expert and CLA expert to help with the rest.

    Cherry Zhou said:
    since the result of multiple adc is required, if the acquisition is placed in the EPWM interrupt, there will be a long delay, resulting in the entire interrupt time well beyond 3 PWM cycles. Is there any other way to sample the ADC?

    You need to configure the ADCs to start the conversion on a tigger. They can sample and hold during the idle time. You can set up the trigger to happen well before the EPWM interrupt occurs.

    The trigger is EPWMx ADCSOCA/B.

    The EPWM interrupt can be on TBPRD/ZERO. The trigger can be configured for CMPA/B/C/D which you can place somewhere before the EPWM PRD occurs.

    By the time the EPWM interrupt occurs all values should be ready.

    Or you can use the ADC interrupts and enable it so that when it happens, all of the conversions are done:

    Cherry Zhou said:
    can CLA be used to reduce the time of the operation because there are many floating-point operations when processing the sampled data?

    You want to use the CLA when the CPU bandwidth is full. The CLA can definitely be used for this. You just have to assign all peripherals needed to the CLA.

    Cherry Zhou said:
    If CLA can be used, then sample + process data + update CMPAs, how should these be set?

    We should have CLA examples showcasing this.

    Cherry Zhou said:
    Set up EPWM1 to generate both ADC SOC trigger signal and EPWM interrupt, ADC trigger first or EPWM interrupt first?

    You should probably as i mentioned trigger the ADC first, generate your EPWM interrupt when you the ADCs are done. OR just use the ADC interrupt as mentioend.

    Cherry Zhou said:
    Does ADC sampling and conversion take up CPU time? 

    No

    I will notify the team to bring in the other reasoureces on ADC and CLA for further help.

  • +1 in reply to Nima Eskandari
    TI__Expert 7715 points

    Hi Cherry,

    Please let me know if you have any further questions.

    Thanks,

    Ashwini