Hi champs,
In F2838x TRM, we have below EOT bit function description of SSICR1 register.
Based on the description above, I have below questions when setting EOT to 1,
- the DMATX bit cannot be set to 1 in any mode. What DMATX bit in which register does it mean here?
- If the bit is kept at 0 during operation, an interrupt is still generated when the TX FIFO is half or less full with or without using the uDMA.EOT(Legacy). What bit does it mean here, is it DMATX bit? Does this mean the interrupt is still generated when TX FIFO is half or less full, even we keep DMATX bit at 0?
- My customer needs a method/interrupt to indicate when the Tx FIFO is empty and the last bit has been transmitted out of the serializer(used with uDMA), what should he does for this request?
Please advise your comments, thanks for help.
Regards,
Luke
