This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280049C: Question about malloc function

Part Number: TMS320F280049C


Dear team:

My client will encounter an exception when calling malloc function. The memory is not allocated and the return value is empty.

Moreover, the customer looked at the map file and did not find the start and end addresses of the heap.

Below is customer's cmd file:

MEMORY
{
PAGE 0: /* Program Memory */
PAGE 1: /* Data Memory */
BEGIN : origin = 0x00080000, length = 0x00000002
BOOT_RSVD : origin = 0x00000002, length = 0x00000126

/* RAMLS5 : origin = 0x0000A800, length = 0x00000800 */
/* RAMLS6 : origin = 0x0000B000, length = 0x00000800 */
/* RAMLS7 : origin = 0x0000B800, length = 0x00000800 */
RAMLS567 : origin = 0x0000A600, length = 0x00001A00

/* Flash sectors */
/* BANK 0 */
/* FLASHBANK0_SECT0 : origin = 0x00080002, length = 0x00000FFE */
FLASHBANK0_BOOT : origin = 0x00080002, length = 0x00000FFE /* remote update */
/* FLASHBANK0_SECT1 : origin = 0x00081000, length = 0x00001000 */
/* FLASHBANK0_SECT2 : origin = 0x00082000, length = 0x00001000 */
/* FLASHBANK0_SECT3 : origin = 0x00083000, length = 0x00001000 */
/* FLASHBANK0_SECT4 : origin = 0x00084000, length = 0x00001000 */
/* FLASHBANK0_SECT5 : origin = 0x00085000, length = 0x00001000 */
/* FLASHBANK0_SECT6 : origin = 0x00086000, length = 0x00001000 */
/* FLASHBANK0_SECT7 : origin = 0x00087000, length = 0x00001000 */
/* FLASHBANK0_SECT8 : origin = 0x00088000, length = 0x00001000 */
/* FLASHBANK0_SECT9 : origin = 0x00089000, length = 0x00001000 */
/* FLASHBANK0_SECT10 : origin = 0x0008A000, length = 0x00001000 */
/* FLASHBANK0_SECT11 : origin = 0x0008B000, length = 0x00001000 */
/* FLASHBANK0_SECT12 : origin = 0x0008C000, length = 0x00001000 */
/* FLASHBANK0_SECT13 : origin = 0x0008D000, length = 0x00001000 */
FLASHBANK0_CODE : origin = 0x00081000, length = 0x0000D000 /* control code */

/* FLASHBANK0_SECT14 : origin = 0x0008E000, length = 0x00001000 */
FLASHBANK0_DATA : origin = 0x0008E000, length = 0x00001000 /* constant data */

FLASHBANK0_SECT15 : origin = 0x0008F000, length = 0x000FF0
FLASHBANK0_SEC15_RSVD : origin = 0x08FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

BOOTROM : origin = 0x003F0000, length = 0x00008000
BOOTROM_EXT : origin = 0x003F8000, length = 0x00007FC0
RESET : origin = 0x003FFFC0, length = 0x00000002

RAMM0S : origin = 0x00000128, length = 0x00000118 /* stack, on-chip RAM block M0 part */
RAMM1D : origin = 0x00000240, length = 0x000005B8 /* on-chip RAM block M0 part & M1 */
RAMM1_RSVD : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

RAMGS0 : origin = 0x0000C000, length = 0x00002000 /**8*16K*/
RAMGS1 : origin = 0x0000E000, length = 0x00002000 /**8*16K*/
RAMGS2 : origin = 0x00010000, length = 0x00002000 /**8*16K*/
RAMGS3 : origin = 0x00012000, length = 0x00001FF8 /**8*16K*/
// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMLS4 : origin = 0x0000A000, length = 0x00000600
}


SECTIONS
{
.reset : > RESET, TYPE = DSECT
codestart : > BEGIN, ALIGN(4)


GROUP
{
#if defined(SFRA_ENABLE)
.TI.ramfunc
{
-l sfra_f32_tmu_eabi.lib<sfra_f32_tmu_collect.obj> (.text)
-l sfra_f32_tmu_eabi.lib<sfra_f32_tmu_inject.obj> (.text)
}
#else
.TI.ramfunc
#endif
ramfuncs
/* Digital Controller Library functions */
dclfuncs
dcl32funcs
} LOAD = FLASHBANK0_CODE
RUN = RAMLS567,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(2)

ctrlfuncs : {
}
LOAD = FLASHBANK0_CODE
RUN = RAMLS567,
LOAD_START(ctrlfuncsLoadStart),
LOAD_SIZE(ctrlfuncsLoadSize),
LOAD_END(ctrlfuncsLoadEnd),
RUN_START(ctrlfuncsRunStart),
RUN_SIZE(ctrlfuncsRunSize),
RUN_END(ctrlfuncsRunEnd),
ALIGN(2)

.text : > FLASHBANK0_CODE, ALIGN(8)
.cinit : > FLASHBANK0_CODE, ALIGN(4)
.switch : > FLASHBANK0_CODE, ALIGN(4)
.cio : > FLASHBANK0_CODE
.pinit : > FLASHBANK0_CODE, ALIGN(4)
.const : > FLASHBANK0_CODE, ALIGN(4)
.init_array : > FLASHBANK0_CODE, ALIGN(4)

.stack : > RAMM0S
.bss : > RAMM1D
.bss:output : > RAMM1D
.bss:cio : > RAMM1D
.data : > RAMM1D
.sysmem : > RAMGS1

est_data : > RAMLS4
}

SECTIONS
{
prms_data : > FLASHBANK0_DATA

GROUP
{
user_data
foc_data
}
LOAD = RAMM1D
LOAD_START(ctrlVarsLoadStart),
LOAD_SIZE(ctrlVarsLoadSize),
LOAD_END(ctrlVarsLoadEnd)

GROUP
{
sys_data
ctrl_data
motor_data
}
LOAD = RAMGS0
LOAD_START(motorVarsLoadStart),
LOAD_SIZE(motorVarsLoadSize),
LOAD_END(motorVarsLoadEnd)


GROUP
{
vibc_data
dmaBuf_data

datalog_data
graph_data

sfra_data
SFRA_F32_Data
}
LOAD = RAMGS0
LOAD_START(extVarsLoadStart),
LOAD_SIZE(extVarsLoadSize),
LOAD_END(extVarsLoadEnd)

GROUP
{
jpf_data
}
LOAD = RAMGS1
LOAD_START(jpfVarsLoadStart),
LOAD_SIZE(jpfVarsLoadSize),
LOAD_END(jpfVarsLoadEnd)
}

Is there anything wrong with that? 

Best regards

  • Hello,

    So I guess the question reduces to "why is the sysmem section not created?" I don't understand why the program would link if this were true.

    Without console output it's difficult to diagnose. The only thing I can spot is that sysmem and jpf_data are both in GSRAM1. Try moving sysmem to LSRAMX.

  • What is the setting of the linker option --heap_size?

    Thanks and regards,

    -George

  • Hi Kier & George:

    Customer has resolved his problem by move .sysmem to LSRAM1.

    Thank you for your support and may I know why can't put .sysmem in GSRAM1? 

  • I should think that in principle you can put sysmem in GSRAM it's just that GSRAM1 might have been blocked for CPU access for some reason in this case. Perhaps CPUWRPROT_GS1 = 1? So I think you have a solution but not root cause. I defer to George for root cause explanations.

  • Green,

    Has the customer looked at the GSxACCPROT0 register?  From reset read/write access from both CPU and DMA should be allowed, but if they have re-configured this to not allow some combination of the above it could result in blocking the CPU from writing per their observation.

    They will also need to make sure the GSx RAMS are initialized before using them.  This should be the same process as the dedicated RAMs, but want to point that out.

    Otherwise, I don't see any other blocking mechanism on this device that would limit the use of the GSx blocks.

    Best,

    Matthew