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16 bit synchronous EMIF bus communicates with FPGA. The problems are as follows:
1. Why are there two write command signals for a write command to the same address?
2. How to write odd addresses?
Hi Chen,
Which example code you are using in this case ?
Since you are doing data access from higher address range, I would suggest to refer to below appnotes.
https://www.ti.com/lit/pdf/sprac96
https://www.ti.com/lit/pdf/spraby4
Regards,
Vivek Singh