Putting the C2000, F2808 into low power Halt mode

There are example projects in the F280x C/C++ Header Files and Peripheral Examples release that illustrate placing the device into HALT mode and then exiting out of it.

In the lpm_haltwake example, it does mention removing the JTAG interface while the device is in HALT mode to measure the lowest power.

Customer has read and believes they are complying with the recommended HALT procedure. Customer has a new question:

On our board we have an external oscillator that generates a 3.3V , square wave  and is  continuously ON, will this prevent the processor going into HALT mode and not reduce current consumption?

New customer questions:

Our Current design uses an external oscillator 

Question 1)  The XCLKIN shows as dead  as per picture, do we need to disable our external oscillator to put the Processor into HALT mode

Question 2)  Can the same GPIO pin be used to  put the processor into HALT mode  and to WAKE up the Processor . For example I plan to use GPIO6  to use to put into HALT and to wake up the processor .

Question 3)  Do you need an Positive going edge to put the processor into HALT, or can it be a Negative edge – Low going signal

Question 4) Do you need a negative going edge to Wake up the processor

Question 5) Can the wake up signal , which as per the picture is a negative going , can be permanently held low , or do we need an signal that remains low and again comes high. Focusing on the section below for the GPIO pin

Question 6) Do we need to manually power down the FLASH ,  or is automatically taken care of when the appropriate mode is selected.

Here is what I would answer:

Q1) not sure, but I would guess that the C2000 will enter the HALT mode regardless of the status of the external clock unit. 

Q2) the processor is forced into HALt by executing the "idle" instruction, so you cannot put the device into Halt directly by an external signal. However, what you can do is to specify a GPIO as external interrupt source (XINT1, XINT2) and use its interrupt service to launch the power down sequence. And, yes you could use the very same GPIO as for the wakeup. Wakeup is falling edge sensitive, the signal must stay low until the oscillator completes power up (page 57 of spru712g). That leaves the riging edge to qualify the GPIO as external interrupt source.

Q3) as mentioned in Q2, the launch signal to enter HALT must be an XINTx - Signal, which can be programmed both to falling or rising edge sensitive. 

Q4) Page 57 of spru712g: falling edge to wakeup from HALT. 

Q5) the wakeup signal is the falling edge. If you keep the signal at permanently at low, it should not matter. To produce a wakeup-signal you need a falling edge, so you have to set it back to 1 before you await a 2nd wakeup.  

Q6)  Yes, you will have to switch the FLASH into low power (register FPWR), before you enter Halt Mode.

Larry,

Most of your questions have been (correctly) answered by Frank Bormann. Let me add a few more points.

You do not need to disable the external clock if you want to HALT the device. However, if you would like to realize the currents shown for the HALT mode in the datasheet, you need to stop the external clock. if you use an external crystal, this is sutomatically taken care of in the design. i.e. the on-chip oscillator is automatically shut down in HALT mode. This, obviously, cannot happen in the case of an external oscillator. The device itself would still go into the HALT mode, but expect to see a 2 or 3 mA of current in the VDDIO rail, in addition to the uA shown in the datasheet.

Having the JTAG connector connected to the device does not prevent the device from going into the HALT mode. However, you will see an additional 2 or 3 mA current in the VDDIO rail if you have the JTAG connector connected. In other words, in order to realize the currents shown in the datasheet, Flash must be powered down (with code running out of RAM, NOT flash), Clock to the device must be killed and the JTAG connector removed.

Hareesh, 

Thanks for your additional comments. 

Customer is running with an external oscillator, that needs to be changed. From their comments below, the currents still seem high to me. 

Is there something else they need to disable or will they get to the sleep currents in the data sheet once the external clock, disable the Flash and disconnect the JTAG probe are implemented? 

In halt mode we are 17.3mA compared to 27.3mA in non halt mode.
We have also experimented on our own design in which the only device on the 1.8V supply is the F2808.
Here we observe 15mA in lower power mode.

Anything on the peripheral bus that can be shut down has been shutdown, see below :

// PERIPHERAL CLOCK ENABLES
//---------------------------------------------------
// If you are not using a peripheral you may want to switch
// the clock off to save power, i.e. set to =0
//
// Note: not all peripherals are available on all 280x derivates.
// Refer to the datasheet for your particular device.

   SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0;    // ADC
   //------------------------------------------------
   SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 0;   // I2C
   //------------------------------------------------
   SysCtrlRegs.PCLKCR0.bit.SPIAENCLK=0;     // SPI-A
   SysCtrlRegs.PCLKCR0.bit.SPIBENCLK=0;     // SPI-B
   SysCtrlRegs.PCLKCR0.bit.SPICENCLK=0;     // SPI-C
   SysCtrlRegs.PCLKCR0.bit.SPIDENCLK=0;     // SPI-D
   //------------------------------------------------
   SysCtrlRegs.PCLKCR0.bit.SCIAENCLK=0;     // SCI-A
   SysCtrlRegs.PCLKCR0.bit.SCIBENCLK=0;     // SCI-B
   //------------------------------------------------
   SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=0;    // eCAN-A
   SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=0;    // eCAN-B
   //------------------------------------------------
   SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 0;  // eCAP1
   SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 0;  // eCAP2
   SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 0;  // eCAP3
   SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 0;  // eCAP4
   //------------------------------------------------
   SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 0;   // ePWM1
   SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 0;   // ePWM2
   SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 0;   // ePWM3
   SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 0;   // ePWM4
   SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 0;   // ePWM5
   SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 0;   // ePWM6
   //------------------------------------------------
   SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 0;   // eQEP1
   SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 0;   // eQEP2
   //------------------------------------------------
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;   // Enable TBCLK
   //------------------------------------------------

Larry,

2 things I can think off:

1) Is EALLOW valid? Did customer actually verify that 0x0002 has been written to the LPMCR0 register?

2) Is the flash really powered down? Does customer's board design have the granularity to measure current into VDD3VFL pin?

Both in HALT & STANDBY modes, clock to ALL peripherals will be automatically turned off, by design. There is no need for code to manually disable the peripheral clocks.