• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 82 subscribers
  • Views 399 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LAUNCHXL-F28069M: CAN Stuff Error Message

Andrew Butler
Expert 2520 points

Part Number: LAUNCHXL-F28069M

I have been running this code for serval months with no issues and I hooked up the CANalyzer today and I get once message transmitted from CANalyzer and received by the microcontroller and then it sends a stuff error message from then on. I haven't changed anything with the code in several weeks and I haven't changed anything with the CAN interface in a month or so.

Here is my CAN config code. What is causing this issue to happen now?

void InitCAN(void)
{
    /* Create a shadow register structure for the CAN control registers.

    This is needed, since, only 32-bit access is allowed to these registers. 16-bit access
     to these registers could potentially corrupt the register contents. This is
     especially true while writing to a bit (or group of bits) among bits 16 - 31 */

   /* Initialize the CAN module */
    InitECan();
    InitECanGpio();

    MessageReceivedCount = 0;

    /* Write to the MSGID field  */

    EALLOW;
        ECanaMboxes.MBOX0.MSGID.all = 0x18FED917;       // Transmit 0x00FED9 (AUXIO1) globally from Linear Load Feedback SA 0x17
        ECanaMboxes.MBOX1.MSGID.all = 0x18FED927;       // Receive 0x00FED9 (AUXIO1) globally from Linear Load GUI SA 0x27
        ECanaMboxes.MBOX2.MSGID.all = 0x18A52717;       // Transmit 0x00A500 (AUXIO4) globally from Linear Load SW Inputs SA 0x17
        ECanaMboxes.MBOX3.MSGID.all = 0x18082717;       // Transmit 0x000800 (AUXIO5) globally from Linear Load PWM Inputs SA 0x17
        ECanaMboxes.MBOX4.MSGID.all = 0x189D2717;       // Transmit 0x009D00 (AUXIO6) globally from Linear Load Analog Inputs SA 0x17
        ECanaMboxes.MBOX5.MSGID.all = 0x189C1727;       // Receive 0x009C00 (AUXIO7) globally from Linear Load GUI SA 0x27
        ECanaMboxes.MBOX6.MSGID.all = 0x189C2717;       // Transmit 0x009C00 (AUXIO7) globally from Linear Load Config SA 0x17

    /* Configure mask for Mailboxes*/
    ECanaLAMRegs.LAM1.all = 0xBF000000;             // MSGID Mask for MBOX1 (RX Linear Load Testbench Control): b10111111000000000000000000000000
    ECanaLAMRegs.LAM5.all = 0xBF000000;             // MSGID Mask for MBOX5 (RX Linear Load Testbench Control): b10111111000000000000000000000000

    /* Configure bit timing parameters for eCANA*/
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;    // Save the (CANMC) Master Control Register
    ECanaShadow.CANMC.bit.CCR = 1 ;                 // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;    // Set the (CANMC) Master Control Register

    // Wait until the CPU has been granted permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;  // Set the (CANES) Error and Status Register
    } while(ECanaShadow.CANES.bit.CCE != 1 );       // Wait for CCE bit to be set..

    ECanaShadow.CANBTC.all = 0;
    /* The following block is for 90 MHz SYSCLKOUT. (45 MHz CAN module clock Bit rate = 1 Mbps
       See Note at end of file. */

    ECanaShadow.CANBTC.bit.BRPREG = 11;             // 2 for 1 Mbps, 5 for 500 kbps, 11 for 250 kbps, 23 for 125 kbps, 29 for 100 kbps
    ECanaShadow.CANBTC.bit.TSEG2REG = 3;            // Time Segement 2 for the Bit Timing Configuration Register (length of the phase in TQ units) TSEG2 = TSEG2reg + 1
    ECanaShadow.CANBTC.bit.TSEG1REG = 9;            // Time Segement 1 for the Bit Timing Configuration Register (length of a bit on the CAN bus) TSEG1 = TSEG1reg + 1

    ECanaShadow.CANBTC.bit.SAM = 1;                 // The CAN module samples three times and make a majority decision.
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;  // Set the (CANBTC) Bit Timing Configuration Register

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;    // Save the (CANMC) Master Control Register
    ECanaShadow.CANMC.bit.CCR = 0 ;                 // Clear CCR = 0: The CPU requests normal operation.
    ECanaShadow.CANMC.bit.ABO = 1;                  // Set ABO = 1: Auto bus on.
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;    // Set the (CANMC) Master Control Register

    // Wait until the CPU no longer has permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;  // Set the (CANES) Error and Status Register
    } while(ECanaShadow.CANES.bit.CCE != 0 );       // Wait for CCE bit to be  cleared..

    /* Configure Mailbox 0 under test as a Transmit mailbox */
    ECanaMboxes.MBOX0.MSGID.bit.IDE = 1;            // Set Mailbox 0 with a 29-bit extended MSGID
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;    // Save the (CANMD) Message Data Register
    ECanaShadow.CANMD.bit.MD0 = 0;                  // Set Mailbox 0 as transmit
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;    // Set the (CANMD) Message Data Register

    /* Enable Mailbox 0 under test */
    ECanaShadow.CANME.all = ECanaRegs.CANME.all;    // Save the (CANME) Mailbox Enable Register
    ECanaShadow.CANME.bit.ME0 = 1;                  // Enable Mailbox 0
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;    // Set the (CANME) Mailbox Enable Register

    /* Configure Mailbox 1 under test as a Recieve mailbox */
    ECanaMboxes.MBOX1.MSGID.bit.IDE = 1;            // Set Mailbox 1 with a 29-bit extended MSGID
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;    // Save the (CANMD) Message Data Register
    ECanaShadow.CANMD.bit.MD1 = 1;                  // Set Mailbox 1 as recieve
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;    // Set the (CANMD) Message Data Register

    /* Enable Mailbox 1 under test */
    ECanaShadow.CANME.all = ECanaRegs.CANME.all;    // Save the (CANME) Mailbox Enable Register
    ECanaShadow.CANME.bit.ME1 = 1;                  // Enable Mailbox 1
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;    // Set the (CANME) Mailbox Enable Register

    /* Configure Mailbox 2 under test as a Transmit mailbox */
    ECanaMboxes.MBOX2.MSGID.bit.IDE = 1;            // Set Mailbox 2 with a 29-bit extended MSGID
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;    // Save the (CANMD) Message Data Register
    ECanaShadow.CANMD.bit.MD2= 0;                   // Set Mailbox 2 as transmit
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;    // Set the (CANMD) Message Data Register

    /* Enable Mailbox 2 under test */
    ECanaShadow.CANME.all = ECanaRegs.CANME.all;    // Set the (CANME) Mailbox Enable Register
    ECanaShadow.CANME.bit.ME2 = 1;                  // Enable Mailbox 2
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;    // Save the (CANME) Mailbox Enable Register

    /* Configure Mailbox 3 under test as a Transmit mailbox */
    ECanaMboxes.MBOX3.MSGID.bit.IDE = 1;            // Set Mailbox 3 with a 29-bit extended MSGID
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;    // Save the (CANMD) Message Data Register
    ECanaShadow.CANMD.bit.MD3= 0;                   // Set Mailbox 3 as transmit
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;    // Set the (CANMD) Message Data Register

    /* Enable Mailbox 3 under test */
    ECanaShadow.CANME.all = ECanaRegs.CANME.all;    // Set the (CANME) Mailbox Enable Register
    ECanaShadow.CANME.bit.ME3 = 1;                  // Enable Mailbox 3
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;    // Save the (CANME) Mailbox Enable Register

    /* Configure Mailbox 4 under test as a Transmit mailbox */
    ECanaMboxes.MBOX4.MSGID.bit.IDE = 1;            // Set Mailbox 4 with a 29-bit extended MSGID
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;    // Save the (CANMD) Message Data Register
    ECanaShadow.CANMD.bit.MD4= 0;                   // Set Mailbox 4 as transmit
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;    // Set the (CANMD) Message Data Register

    /* Enable Mailbox 4 under test */
    ECanaShadow.CANME.all = ECanaRegs.CANME.all;    // Set the (CANME) Mailbox Enable Register
    ECanaShadow.CANME.bit.ME4 = 1;                  // Enable Mailbox 4
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;    // Save the (CANME) Mailbox Enable Register

    /* Configure Mailbox 5 under test as a Recieve mailbox */
    ECanaMboxes.MBOX5.MSGID.bit.IDE = 1;            // Set Mailbox 5 with a 29-bit extended MSGID
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;    // Save the (CANMD) Message Data Register
    ECanaShadow.CANMD.bit.MD5 = 1;                  // Set Mailbox 5 as recieve
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;    // Set the (CANMD) Message Data Register

    /* Enable Mailbox 5 under test */
    ECanaShadow.CANME.all = ECanaRegs.CANME.all;    // Save the (CANME) Mailbox Enable Register
    ECanaShadow.CANME.bit.ME5 = 1;                  // Enable Mailbox 5
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;    // Set the (CANME) Mailbox Enable Register

    /* Write to DLC field in Master Control reg */
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;          // Set the DLC to 8 Bytes for Mailbox 0
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;          // Set the DLC to 8 Bytes for Mailbox 1
    ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;          // Set the DLC to 8 Bytes for Mailbox 2
    ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;          // Set the DLC to 8 Bytes for Mailbox 3
    ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;          // Set the DLC to 8 Bytes for Mailbox 4
    ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;          // Set the DLC to 8 Bytes for Mailbox 5

        ECanaRegs.CANMIL.bit.MIL1=0;                // Clear the Mailbox Interrupt Level bit
        ECanaRegs.CANGIM.bit.I0EN=1;                // Set the Global Mailbox Interrupt Mask bit
        ECanaRegs.CANMIM.all = 0x00000022;          // Set the Mailbox Interrupt Mask Register for Mailbox 1
    EDIS;
}

  • +1
    TI__Mastermind 39700 points

    Hi Andrew,

    Did anything change in the hardware (CAN bus wiring, additional load, clock source..etc)?  Stuffing error is kind of hard to produce as the error has to occur in the right position to mask a bit.  In CAN frame, the bit stream is automatically padded (stuffed) with an extra bit of opposite state whenever a series of 5 consecutive bits of the same polarity are detected by the transmitting module.  Hence i'm asking if there was a change in hardware that might have caused this.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Expert 2520 points

    The only things I can think of that changed was the fact that I damaged a F28069M and I am using a different one now. This cant be the problem because I have damaged multiple boards before and have changed to new ones multiple times with no issues. Another thing that changed was the fact that I moved the folder containing the source file for this code to another location and now using it from the new location. I don't know if it is possible that all of the files didn't get moved or something. I did notice that CCS couldn't locate the ROV file for debugging purposes so I just regenerated one and now that is working but maybe something else is missing that I am unaware of.

  • 0 in reply to Joseph Casuga
    Expert 2520 points

    I had another launchpad laying around. I tried that and my code is working again. So apparently that first board I switched to had issues with the CAN controller even though the rest of the software seemed to be working. Thanks for you help!