Linker fails for trampoline call problem.

Phil Gillaspy

Part Number: TMS320F280049C

My CCS project has been compiling fine up until I had to integrate someone else's code with my project. The linker is failing with the following error:

<Linking>
"../device/c280049C_MCE_FLASH.cmd", line 72: error #10099-D: program will not fit into available memory, or the section contains a call site that requires a trampoline that can't be generated for this section. placement with alignment/blocking fails for section ".cinit" size 0x1227 page 0. Available memory ranges:
   FLASH_BANK0_SEC1   size: 0x1000       unused: 0x1000       max hole: 0x1000
   FLASH_BANK0_SEC2   size: 0x1000       unused: 0x1000       max hole: 0x1000
   FLASH_BANK0_SEC3   size: 0x1000       unused: 0x1000       max hole: 0x1000
error #10010: errors encountered during linking; "MCE.out" not built

I do not believe it has to do with .cinit not having enough memory as it has allocated three 4K memory flash memory banks. I strongly suspect that it has to do with a trampoline call problem. I don't know how to identify what the trampoline is. Wondering if someone can have compassion and help me out. Let me know what other information I should supply.

over 3 years ago

0 Phil Gillaspy over 3 years ago

Prodigy 210 points

Update: command file follows -

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN              : origin = 0x080000, length = 0x000002
   RAMM0              : origin = 0x0000F6, length = 0x00030A

   RAMLS0             : origin = 0x008000, length = 0x000800
   RAMLS1             : origin = 0x008800, length = 0x000800
   RAMLS2             : origin = 0x009000, length = 0x000800
   RAMLS3             : origin = 0x009800, length = 0x000800
   RAMLS4             : origin = 0x00A000, length = 0x000800
   RESET              : origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   /* BANK 0 */
   FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE   /* on-chip Flash */
   FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000   /* on-chip Flash */

   /* BANK 1 */
   FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000   /* on-chip Flash */
   FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000   /* on-chip Flash */

PAGE 1 :

   BOOT_RSVD   : origin = 0x000002, length = 0x0000F3     /* Part of M0, BOOT rom will use this for stack */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */

   RAMLS5      : origin = 0x00A800, length = 0x001800

   RAMGS0      : origin = 0x00C000, length = 0x002000
   RAMGS1      : origin = 0x00E000, length = 0x002000
   RAMGS2      : origin = 0x010000, length = 0x002000
   RAMGS3      : origin = 0x012000, length = 0x002000
}

SECTIONS
{
   codestart        : > BEGIN,     PAGE = 0, ALIGN(4)
   .text            : >>FLASH_BANK0_SEC1|FLASH_BANK0_SEC2|FLASH_BANK0_SEC3|FLASH_BANK0_SEC4|FLASH_BANK0_SEC5|FLASH_BANK0_SEC6|FLASH_BANK0_SEC7|FLASH_BANK0_SEC8|FLASH_BANK0_SEC9|FLASH_BANK0_SEC10,   PAGE = 0, ALIGN(4)
   .cinit           : > FLASH_BANK0_SEC0|FLASH_BANK0_SEC1|FLASH_BANK0_SEC2|FLASH_BANK0_SEC3,   PAGE = 0, ALIGN(4)
   .pinit           : > FLASH_BANK0_SEC1,     PAGE = 0, ALIGN(4)
   .switch          : > FLASH_BANK0_SEC1,     PAGE = 0, ALIGN(4)
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM1,     PAGE = 1

   .init_array      : > FLASH_BANK0_SEC1,       PAGE = 0,       ALIGN(4)
   .bss             : > RAMLS5 /*,       PAGE = 0 */
   .bss:output      : > RAMLS3 /* ,       PAGE = 0 */
   .bss:cio         : > RAMLS0 /* ,       PAGE = 0 */
   .data            : > RAMLS5 /* ,       PAGE = 0 */
   .sysmem          : > RAMLS5 /* ,       PAGE = 0 */
   /* Initalized sections go in Flash */
   .const           : > FLASH_BANK0_SEC4,       PAGE = 0,       ALIGN(4)

   .ebss            : > RAMLS5,       PAGE = 1
   .esysmem         : > RAMLS5,       PAGE = 1
   .cio             : > RAMLS0,       PAGE = 0
   .econst          : > FLASH_BANK0_SEC4,    PAGE = 0, ALIGN(4)

   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1

   /* Allocate IQ math areas: */
   IQmath           : > RAMGS2,    PAGE = 1            /* Math Code */
   IQmathTables     : > RAMGS3,    PAGE = 1
    .TI.ramfunc : {} LOAD = FLASH_BANK0_SEC1,
                         RUN = RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)

   rts_lib
   {
      --library=rts2800_fpu32.lib(.text)
      rt_nonfinite.obj(.text)
      rtGetInf.obj(.text)
      rtGetNaN.obj(.text)
   } > FLASH_BANK0_SEC3|FLASH_BANK0_SEC4

   UNION run = FLASH_BANK0_SEC7, PAGE = 0
   {
      PieVectTableFile
      GROUP
      {
         EmuKeyVar
         EmuBModeVar
         FlashCallbackVar
         FlashScalingVar
      }
   }

   AdcaResultRegsFile    : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   AdcbResultRegsFile    : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   AdccResultRegsFile    : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT

   AdcaRegsFile          : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   AdcbRegsFile          : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   AdccRegsFile          : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT

   PieCtrlRegsFile       : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   InputXbarRegsFile     : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   EQep1RegsFile         : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   GpioCtrlRegsFile      : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   CpuSysRegsFile        : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   GpioDataRegsFile      : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   AnalogSubsysRegsFile : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT

   EPwm1RegsFile         : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   EPwm2RegsFile         : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   EPwm3RegsFile         : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   EPwm4RegsFile         : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   EPwm5RegsFile         : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   EPwm6RegsFile         : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   EPwm7RegsFile         : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT
   EPwm8RegsFile         : > FLASH_BANK0_SEC7,   PAGE = 0, type=NOINIT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 Veena Kamath over 3 years ago in reply to Phil Gillaspy

TI__Mastermind 32565 points

Hi,

The .cinit section cannot be split and placed in different memory blocks like

.cinit : > FLASH_BANK0_SEC0|FLASH_BANK0_SEC1|FLASH_BANK0_SEC2|FLASH_BANK0_SEC3

If a sinfle memory block is not enough, you can combine 2 or more memory blocks to form a larger memory block.

Eg:

// FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */

FLASH_BANK1_SEC0_1 : origin = 0x090000, length = 0x002000 /* on-chip Flash */

.cinit : > FLASH_BANK1_SEC0_1

Regards,

Veena

0 Phil Gillaspy over 3 years ago in reply to Veena Kamath

Prodigy 210 points

I ended up combining the 15 individual 4K blocks into a single FLASH_BANK. Linker was happy after that.

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Linker fails for trampoline call problem.