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TMS320F28384D: Atomic operations or mutexes for C28x1/CM shared memories

Valerio De Benedetto
Prodigy 10 points

Part Number: TMS320F28384D

Hi, in my project I'm using both CPU1TOCMMSGRAM and CMTOCPU1MSGRAM to share data between CPU1 and CM. At any moment one core should be able to read any data from the shared memory owned by the other one (i'm not using the message-based API exposed by driverlib). This is working fine, but I was having some doubts about data access concurrency.

My two questions are:

- Is there any kind of IPC lock, like a mutex, that blocks the other core from reading data while the owner core is writing it? Even a "global" lock could be useful in my case

- If the above does not exist, and since i'm sharing only 16-32 bit values, is the store of these values atomic for both CPU architectures? I.e, can I read a 32bit value from one side, while is the other is updating it, without reading garbage?

Thank you for your answers in advance

  • 0
    TI__Guru 55700 points

    Valerio,

    Valerio De Benedetto said:
    - Is there any kind of IPC lock, like a mutex, that blocks the other core from reading data while the owner core is writing it? Even a "global" lock could be useful in my case

    No, this feature is not available.

    Valerio De Benedetto said:
    - If the above does not exist, and since i'm sharing only 16-32 bit values, is the store of these values atomic for both CPU architectures? I.e, can I read a 32bit value from one side, while is the other is updating it, without reading garbage?

    No, there is a possibility to read garbage data from one core when another core is updating data. The only way to get around this is to use IPC flags to let other CPU know that it is safe to read the MSGRAM contents (ie after the write operation was completed by other CPU)

    Regards,

    Manoj