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TMS320F2808: erasing failure rate

Renan Santos Adriano
Mastermind 26295 points

Part Number: TMS320F2808

Hello Team,

My customer applies the chip TMS320F2808 for motor control unit. We found out that there is a 3% failure rate during the erasing sector process in the factory.  So we need to deep dive on this topic.

I searched the datasheet for erasing failure rate. But I didn't discover it. Can you share with us information about erasing failure rate?

Regards,

Renan

  • 0
    TI__Guru* 85620 points

    Renan,

    One of the most common reasons for a device to fail the erase procedure is due to timeout from the customer's system before the operation is completed.  According to the DS each sector can have a max erase time of 15s on this device(the TYP is 2s).  Environmental conditions such as temperature will have an effect on this as well, colder temperatures result in longer erase times.

    Please ask the customer to verify that the system is allowing adequate time for the erase procedure to complete across all sectors/devices.  If they are allowing for the max time we can debug further.

    Also, customer can consider that all devices come in erased state from TI, so if they are doing only one programming in their factory on new devices from TI, there is no need to erase the flash in this condition.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Mastermind 26295 points

    Hello Matthew,

    Our customer replied that the timeout of erase process is 2min30sec in their system. Actually, they explain that they can not sure the cause of the failure, it is maybe caused by cable interference, wrong configuration, etc. But they need rate of erase process to refer. For example, if TI provides the failure rate is much lower than 3%, they will investigate the other potential cause.

    BTW, the chip is programmed first by their sub supplier for their production line testing. So customer has to program again.

    Regards,

    Renan

  • 0 in reply to Renan Santos Adriano
    TI__Guru* 85620 points

    Renan,

    All devices are tested before leaving TI to ensure proper operation to meet the datasheet. So we do not expect any erase failures should happen for the customer from a chip level perspective.  So 3% is worth investigating the root cause, it should be 0%.

    When customer has issue erasing, do we know if device will eventually erase with re-try or is the device permanently failing erase operation?  If erase operation is interrupted a potential issue is that the flash array is left in a metastable state, and that the CSM passwords are programmed to an non 0xFFFF value, locking the device.  If customer can eventually erase the devices, then this is not happening which is a good thing.

    The other thing to look at would be that the VDDIO/VDD3FL supply is stable during flashing operation and staying within the DS specification/tolerance.

    Best,

    Matthew