Hi, run into following problem.
There does not seem to be a way to detect easily and without polling following conditions:
1) All bytes inte the I2C FIFO have been transmitted.
2) The STOP condition has been generated and complete.
Yes, I get an interrupt when the TX FIFO is empty. Also I can get an interrupt when the tramit register contents have been moved to the shift register.
But that happens as soon as the last byte starts to be shifted out, not when it has been shifted out AND importantly the interrpt happens before the ACK/NACK bit has been detected by the I2C interface.
Now, this is a problem because the next message can depend on weather the previous message was NACKed or ACKed.
Further I can't (must not) request the STOP condition to be generated before the last byte has been sent.
So where am I supposed to generate the STOP condition when there is no interrupt to hook to.
And it gets worse, where do I start the next transmission when there is no interrupt that tell the STOP condition generation in the hardware has completed.
I tried the STOP detected interrupt and the corresponding flag polling but I could not get that to work reliably. Sometimes it worked, sometimes not.
(there is strange note on the datasheet that say I need to wait for as long as the longest message before I communicate for the bus busy bit to be reliable, I don't get that either, but maybe this is not related to this question.
As a side note, I need to tallk to several I2C devices with different addresses and some of them reqularly NACK messages.
So what am I missing, this can't be that cumbersome border line design flaw?
I must be doing something wrong but I'm stuck at how to implement this efficiently, without polling, handling NACKs as they come and getting the messages moving back to back.''