TMS320F280025C: Required information about the synchronizer of LIN Module

Hi Quy,

Below are details on your questions:

• Length of the counter register in the controller [bit]
  
  • There are internal counters that are clocked by SYSCLK, which will check the time difference between rise and fall transition of the sync field (i.e. 0x55) and based on the internal counter values will compute the adjusted baud rate.
  • If the Sync break is >13TBIT it will give an error, so max baud rate above the configured baud rate that can be tolerated is ~10%.
• Number of measured bits from the sync field
  • Sync field is 8-bit wide and has to be 0x55
• Count frequency [MHz]
  • Counter frequency is equal to SYSCLK frequency
• Trimming the integrated oscillator?
  • There is no internal oscillator to LIN, not sure on your question? There is not oscillator to trim, unless you are asking about INTOSC which has +/-3% accuracy.
• Minimum baud rate of the synchronization area [Bit/s] (I think it is the setting with MBRSR Register)
  
  • MBRSR register is 13 bit register, so for a SYSCLK of 100MHz, maximum baud rate that can be configured in adaptive mode is 100/8192=12.2Khz, so actual minimum baud rate can be 10% lower than 12.2KHz, which will be ~11KHz.
  • But if you are not using Adaptive mode that baud rate can be configured as low as 1Khz.
• Maximum baud rate of the synchronization area [Bit/s] (I think it is the setting with MBRSR Register)
  
  • 20KHz+10%, which is ~22Khz
• Error when measuring [%]
  • It is a digital logic, so any error in the SYSCLK which is introduced by Crystal or INTOSC will be the error of measurement.
• Calculation error [%]
  • This will be ~1/16 of Sysclk (it is the resolution of the baud rate calculator).
• Setting error [%]
• Maximum baudrate tolerance[%]
  • Maximum Baud rate will have to be within 10% of the actual baud rate configured.

May I know what is your application and what are your requirements?

Best Regards,

Nirav

Hello Nirav,

Thank you for the answer.

My company develops the LIN device for the OEM like VW, BWM, ... I have to fill in their questionaire.

I'd like to add some questions in green:

• Length of the counter register in the controller [bit]
  
  • There are internal counters that are clocked by SYSCLK, which will check the time difference between rise and fall transition of the sync field (i.e. 0x55) and based on the internal counter values will compute the adjusted baud rate.
  • If the Sync break is >13TBIT it will give an error, so max baud rate above the configured baud rate that can be tolerated is ~10%.
    • I'd like to know if you use 16 bit counter or 32 bit counter.
    • If you use SYSCLK (up to 100MHz) to count 8 bits at typical baud rate in LIN (19200), ideally you'll get 41666,67. It will be rounded down to 41666 in your counter. 16bit counter is enough for that. But if you count at 10kbps, you'll get 80000 in the counter => I suppose that you use 32bit counter. Please confirm that.
• Trimming the integrated oscillator?
  • There is no internal oscillator to LIN, not sure on your question? There is not oscillator to trim, unless you are asking about INTOSC which has +/-3% accuracy.
    • I'm not familiar with trim function but I see in Page543/SPRUIN7A: Load INTOSC Trims (12us). Could you please explain more about that. How can the µC calibrate the frequency with this value?
• Minimum baud rate of the synchronization area [Bit/s] (I think it is the setting with MBRSR Register)
  
  • MBRSR register is 13 bit register, so for a SYSCLK of 100MHz, maximum baud rate that can be configured in adaptive mode is 100/8192=12.2Khz, so actual minimum baud rate can be 10% lower than 12.2KHz, which will be ~11KHz.
  • But if you are not using Adaptive mode that baud rate can be configured as low as 1Khz.
    • Suppose that I set the baud rate at 19200bps. If I set MBRSR = 100MHz/(19200*1.1), can my SW synchronize with the bus baudrate in range from (19200*0.9) to (19200*1.1) or from 0 to (19200*1.1)? The under boudary is what I want to know.
• Error when measuring [%]
  
  • It is a digital logic, so any error in the SYSCLK which is introduced by Crystal or INTOSC will be the error of measurement.
    • I think beside the measuring error in INTOSC -2% .. +1.5% (SPRSP45B, Section 7.11.3.5.1), we also have the error from rounding down (1LSB) or trigger error (I don't know how much)
• Calculation error [%]
  • This will be ~1/16 of Sysclk (it is the resolution of the baud rate calculator). 
    • Could you please share how your HW calculate baudrate register from the counter value?
    • If I synchronize with SW, I will do as following: 8 bit time = (counter value) = 8*16*(P+1+M/16)
    • if baud rate = 19200, counter value = 41666 => P=round down(counter value/8/16 - 1) = 324 and M = round down{[counter value- 8*16*(P+1)]/8} = 8
      
    • Does the HW calculate like my formula or you have better calculation with floating point type?

Hi Quy,

Please find my responses in-line:

• Length of the counter register in the controller [bit]
  
  • There are internal counters that are clocked by SYSCLK, which will check the time difference between rise and fall transition of the sync field (i.e. 0x55) and based on the internal counter values will compute the adjusted baud rate.
  • If the Sync break is >13TBIT it will give an error, so max baud rate above the configured baud rate that can be tolerated is ~10%.
    • I'd like to know if you use 16 bit counter or 32 bit counter.
    • If you use SYSCLK (up to 100MHz) to count 8 bits at typical baud rate in LIN (19200), ideally you'll get 41666,67. It will be rounded down to 41666 in your counter. 16bit counter is enough for that. But if you count at 10kbps, you'll get 80000 in the counter => I suppose that you use 32bit counter. Please confirm that.
    • [Nirav] - Yes counter is 32-bit wide to support baud rate as low as 1KBPS
• Trimming the integrated oscillator?
  • There is no internal oscillator to LIN, not sure on your question? There is not oscillator to trim, unless you are asking about INTOSC which has +/-1.5% accuracy.
    • I'm not familiar with trim function but I see in Page543/SPRUIN7A: Load INTOSC Trims (12us). Could you please explain more about that. How can the µC calibrate the frequency with this value?
    • [Nirav] Load INTOSC trims is mainly to load the INTOSC trims on powerup along with other analog trims. This has nothing to do with LIN. By loading the trims we can achieve +/-1.5% accuracy on INTOSC at 10Mhz.
• Minimum baud rate of the synchronization area [Bit/s] (I think it is the setting with MBRSR Register)
  
  • MBRSR register is 13 bit register, so for a SYSCLK of 100MHz, maximum baud rate that can be configured in adaptive mode is 100/8192=12.2Khz, so actual minimum baud rate can be 10% lower than 12.2KHz, which will be ~11KHz.
  • But if you are not using Adaptive mode that baud rate can be configured as low as 1Khz.
    • Suppose that I set the baud rate at 19200bps. If I set MBRSR = 100MHz/(19200*1.1), can my SW synchronize with the bus baudrate in range from (19200*0.9) to (19200*1.1) or from 0 to (19200*1.1)? The under boudary is what I want to know.
    • [Nirav] If you want balanced tolerance on both sides, you can only achieve +/-5% this can be done by setting MBRSR=100Mhz/(19200*1.05) and BRSR=100Mhz(19200*0.95), with an operating baud rate of 19200.
• Error when measuring [%]
  
  • It is a digital logic, so any error in the SYSCLK which is introduced by Crystal or INTOSC will be the error of measurement.
    • I think beside the measuring error in INTOSC -2% .. +1.5% (SPRSP45B, Section 7.11.3.5.1), we also have the error from rounding down (1LSB) or trigger error (I don't know how much)
    • [Nirav] You are right digitization error/rounding error will be +/-1 1 SYSCLK which is 10ns for a 100MHz clock, which will be 0.0192% for a baud rate of 19200.
• Calculation error [%]
  • This will be ~1/16 of Sysclk (it is the resolution of the baud rate calculator). 
    • Could you please share how your HW calculate baudrate register from the counter value?
    • If I synchronize with SW, I will do as following: 8 bit time = (counter value) = 8*16*(P+1+M/16)
    • if baud rate = 19200, counter value = 41666 => P=round down(counter value/8/16 - 1) = 324 and M = round down{[counter value- 8*16*(P+1)]/8} = 8
      
    • Does the HW calculate like my formula or you have better calculation with floating point type?
    • [Nirav] If you need a baud rate of 19200 i.e. 19.2KHz, so (P+1+M/16)*16 = 100M/19.2K= 5208.33; P+1+M/16 = 5208.33/16=325.52; P=324, M=8, which will give you closest frequency to 19.2KHz.

Best Regards,

Nirav

Hello Nirav,

Thank you for the reply. I still have 2 comments:

• Minimum baud rate of the synchronization area [Bit/s] (I think it is the setting with MBRSR Register)
  
  • MBRSR register is 13 bit register, so for a SYSCLK of 100MHz, maximum baud rate that can be configured in adaptive mode is 100/8192=12.2Khz, so actual minimum baud rate can be 10% lower than 12.2KHz, which will be ~11KHz.
  • But if you are not using Adaptive mode that baud rate can be configured as low as 1Khz.
    • Suppose that I set the baud rate at 19200bps. If I set MBRSR = 100MHz/(19200*1.1), can my SW synchronize with the bus baudrate in range from (19200*0.9) to (19200*1.1) or from 0 to (19200*1.1)? The under boudary is what I want to know.
    • [Nirav] If you want balanced tolerance on both sides, you can only achieve +/-5% this can be done by setting MBRSR=100Mhz/(19200*1.05) and BRSR=100Mhz(19200*0.95), with an operating baud rate of 19200.
    • I don't really think so. Last time I set the registers as MBRSR=100Mhz/(19200*1.05) and BRSR=100Mhz(19200*1), then I can see that the µC can synchronize with baudrate < 19200. I will test again today to get the practical value.
• Calculation error [%]
  • This will be ~1/16 of Sysclk (it is the resolution of the baud rate calculator). 
    • Could you please share how your HW calculate baudrate register from the counter value?
    • If I synchronize with SW, I will do as following: 8 bit time = (counter value) = 8*16*(P+1+M/16)
    • if baud rate = 19200, counter value = 41666 => P=round down(counter value/8/16 - 1) = 324 and M = round down{[counter value- 8*16*(P+1)]/8} = 8
      
    • Does the HW calculate like my formula or you have better calculation with floating point type?
    • [Nirav] If you need a baud rate of 19200 i.e. 19.2KHz, so (P+1+M/16)*16 = 100M/19.2K= 5208.33; P+1+M/16 = 5208.33/16=325.52; P=324, M=8, which will give you closest frequency to 19.2KHz.
    • I would like to know how you calculate the baudrate from the value of synchronizer counter. Calculate directly from SYSCLK is only applied for the case without synchronization.
      

Regards,

Quy

Hello Nirav,

I'd like to update the point with MBRS. I tested today with different values of MBRSR and same value of BRSR for 19200 P=324 M=8

• MBRSR = 100MHz/18000: µC can synchronize with baudrate on LIN Bus in range 15860..21400
• MBRSR = 100MHz/19200: µC can synchronize with baudrate on LIN Bus in range 16910..22820
• MBRSR = 100MHz/20000: µC can synchronize with baudrate on LIN Bus in range 17628..23785
• MBRSR = 100MHz/21000: µC can synchronize with baudrate on LIN Bus in range 18512..25000

Is there any fomular to calculate this range from value of MBRSR?

Regards,

Quy

/cfs-file/__key/communityserver-discussions-components-files/171/MBRSR100_5F00_21000.bmp

/cfs-file/__key/communityserver-discussions-components-files/171/MBRSR100_5F00_20000.bmp

/cfs-file/__key/communityserver-discussions-components-files/171/MBRSR100_5F00_19200.bmp

/cfs-file/__key/communityserver-discussions-components-files/171/MBRSR100_5F00_18000.bmp

Hi Quy,

I am confused, are you saying you configured BRSR to 19200 baud rate, and Max Baud rate (MBRSR) to 18000, and you are still able to successfully receive the packet by changing the LIN Bus range from 15860 to 21400?

Best Regards,

Nirav

Hi Nirav,

Yes. I tested with the tools for LIN Conformance Test. if you don't have tool, you can use function generator to generate LIN header for your desired baud rate.

MBRSR = 100*10^6/18000 = 5555

From my measurement, there are linear formula for this range max baud = 1.2 * baudrate of MBRSR and min baud = 0.8 * baudrate of MBRSR

Could you please confirm them?

Regards

Quy

Hi Quy,

By design guidelines, the MBRSR register should not be configured with more than 10% of the operating baud rate (BRSR), it may still work beyond configured value under nominal conditions but it is not guaranteed to work across process/voltage/temperature and is not recommended.

Best Regards,

Nirav

Hi Nirav,

Thank you for the reply.

Unfortunely it's not what I'm concerning about.

Currently I don't have the formula. If I configure as the guidline (not more than 10%), I can configure MBRSR at 21k (not more than 10% of 19200). And then my device can synchronize in range 18512..25000 (-4%..30% of norminal baudrate).

I'm pretty sure that VW won't accept this weird range.

Regards,

Quy