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TMS320F280039C: Is it possible to trigger CLB by communication peripherals?

Wayne Huang
Genius 16805 points

Part Number: TMS320F280039C

Dear Champs,

I am asking this for our customer.

Is it possible to use communication peripheral to trigger CLB?

For example, I2C stop bit to trigger CLB and then use CLB to check I2C RX buffer with some logic combination?

For example, SCI stop bit to trigger CLB and then use CLB to check SCI RX buffer with some logic combination?

DMA may be used as well.

The goal is to reduce CPU loading and use peripheral/CLB/DMA a routine check on its data.

Do you have any idea or suggestion?

Wayne Huang

 

  • 0
    TI__Genius 10845 points

    Hi,

    This query has been assigned to the expert. Please expect delay in response due to the US holiday on Monday.

    Thanks
    Vasudha

  • 0 in reply to Vasudha Bhadoria
    TI__Mastermind 20591 points

    Hi Wayne,

    There are a few communication peripherals that the CLB has direct access to, which include FSI and SPI. The CLB cannot directly connect to I2C or SCI, except for the SCI TX signal.

    What data checks is the customer wanting to perform? An alternative could be to software trigger the CLB using the CLB's GPREG bits.

    Regards,

    Peter

  • 0 in reply to Peter Luong
    TI__Genius 16805 points

    Dear Peter,

    They are more interested in I2C and UART (SCI or LIN@SCI mode) and see if CLB can help reduce CPU loading here.

    For example, if they see the STOP bit, they can use CLB AND/OR/XOR for SCI RX or if they see the ACK bit they can use CLB AND/OR/XOR for I2C RX and then trigger CPU if the result matches something.

    The goal is to replace some routine if/else statements in CPU SCI RX ISR or I2C ISR.

    What do you mean by software trigger the CLB using the CLB's GPREG bits? Does it need CPU's intervention?

    Do you think it's possible?

    Wayne Huang 

  • 0 in reply to Wayne Huang
    TI__Mastermind 20591 points

    Hi Wayne,

    Thank you for the additional details. Each CLB tile has a GPREG register which is 8-bits long and each bit is connected to one of the 8 inputs of the CLB tile. These bits can be manually set through software as either high or low by calling

    CLB_setGPREG(uint32_t base, uint32_t gpRegVal)

    or the below for even more reduced latency

    HWREG(base + CLB_LOGICCTL + CLB_O_GP_REG) = gpRegVal;

    What can be potentially done is whenever the STOP or ACK bit is received, you use the software trigger to simulate the STOP or ACK bit within the CLB. You would then have to use the CLB's FIFO to transfer the I2C or SCI buffer data into the CLB for processing. After it's been processed, you would have to use this same FIFO to transfer data out of the CLB.
    I reviewed the CLB output override table in the TRM and SCIA RX is available to be overriden by the output of the CLB, per the table below
    The customer can try experimenting with this and using the SCI RX output override to eliminate the need to use the FIFO to transfer the data out of the CLB.
    Please let me know if there are any other questions.
    Regards,
    Peter
  • 0 in reply to Peter Luong
    TI__Genius 16805 points

    Dear Peter,

    What do you mean by "What can be potentially done is whenever the STOP or ACK bit is received, you use the software trigger to simulate the STOP or ACK bit within the CLB. "?

    Does that mean the user still needs an ISR to use CPU to trigger CLB during run time for STOP or ACK?

    Wayne Huang

  • 0 in reply to Wayne Huang
    TI__Mastermind 20591 points

    Hi Wayne,

    Yes, that is correct. The software trigger would need to be called within the ISR function that handles the STOP or ACK signal. 

    Regards,

    Peter

  • +1 in reply to Peter Luong
    TI__Genius 16805 points

    Dear Peter

    As it still needs CPU/ISR to handle this during run time, it is not what the user wants because the purpose is to use CLB to offload CPU’s loading for routine check for I2C/SCI  

    thank you for your information anyway  


    Wayne Huang