Part Number: TMS320F280049C
Hi expert,
My customer use F280049 in an LLC topology. they change the frequency and duty at the same time.
EPWM1 is used as the reference timing, EPWM2 and EPWM3 are used as wave generating units to drive the power device. In the process of application, the Global Load function is used to synchronize the time base and duty of EPWM1, EPWM2 and EPWM3 update point.
the PWM frequecncy is from 40kHz to 90KHZ, and the control frequency is fixed at 20KHZ.
In the recent product test, the machine was frequently bombed. I went back to the independent platform to simulate the wave timing. I found that in the process of frequency conversion, there will be a case of a large DUTY pulse at an uncertain time.
At this time, the working condition is that the frequency is 40K, When the width is 0% (or 8%), the frequency is changed to 64K, and the pulse width is 43%, the above phenomenon occurs, and it is happened on PWM2A and PWM3A.
CH1 -EPWM2A ,CH2-EPWM2B, CH3-EPWM3A, CH4-EPWM3B
I have go through the PWM configuration and run time code, I did not find the root cause, could you kindly help to give some ideas?
void DcdcPwmOnOff(void)
{
static Uint16 suwPwmDelayOutCnt = 0;
static Uint16 suwPwmDelayOutFlag = FALSE;
if((0 != stSysFaultMsg.all)||(TRUE == stPwmOnOff.uwTzFlag))
{
stPwmOnOff.unPwmCtrlFlag.bit.LLCEnable = FALSE;
}
else
{
if((cNormalMode == stStatusPara.uwSysMode) && (TRUE == uwAllowLlcDrvFlag))
{
stPwmOnOff.unPwmCtrlFlag.bit.LLCEnable = TRUE;
}
else
{
stPwmOnOff.unPwmCtrlFlag.bit.LLCEnable = FALSE;
}
}
//------------------pwm out on off-----------------------
if(TRUE == stPwmOnOff.unPwmCtrlFlag.bit.LLCEnable)
{
EPwm1Regs.TBPRD = stBuckBoostCtrlPara.fLLCFreq;
EPwm2Regs.TBPRD = stBuckBoostCtrlPara.fLLCFreq;
EPwm3Regs.TBPRD = stBuckBoostCtrlPara.fLLCFreq;
// EPwm2Regs.DBRED.bit.DBRED = (stBuckBoostCtrlPara.fLLCFreq - stBuckBoostCtrlPara.fLLCLowSideDuty * 2);
// EPwm2Regs.DBFED.bit.DBFED = (stBuckBoostCtrlPara.fLLCFreq - stBuckBoostCtrlPara.fLLCLowSideDuty * 2);
// EPwm2Regs.CMPA.bit.CMPA = stBuckBoostCtrlPara.fLLCFreq * 0.5;
// EPwm3Regs.DBRED.bit.DBRED = (stBuckBoostCtrlPara.fLLCFreq - stBuckBoostCtrlPara.fLLCHighSideDuty * 2);
// EPwm3Regs.DBFED.bit.DBFED = (stBuckBoostCtrlPara.fLLCFreq - stBuckBoostCtrlPara.fLLCHighSideDuty * 2);
// EPwm3Regs.CMPA.bit.CMPA = stBuckBoostCtrlPara.fLLCFreq * 0.5;
EPwm2Regs.CMPA.bit.CMPA = stBuckBoostCtrlPara.fLLCLowSideDuty;
EPwm2Regs.CMPB.bit.CMPB = stBuckBoostCtrlPara.fLLCFreq - stBuckBoostCtrlPara.fLLCLowSideDuty; //
EPwm3Regs.CMPA.bit.CMPA = stBuckBoostCtrlPara.fLLCHighSideDuty;
EPwm3Regs.CMPB.bit.CMPB = stBuckBoostCtrlPara.fLLCFreq - stBuckBoostCtrlPara.fLLCHighSideDuty; //
EPwm1Regs.GLDCTL2.bit.OSHTLD = 1; // 同步更新使能
// EPWM_setGlobalLoadOneShotLatch(EPWM1_BASE);
if(FALSE == suwPwmDelayOutFlag)
{
EPwm2Regs.AQCSFRC.all = AQ_NO_ACTION;
EPwm3Regs.AQCSFRC.all = AQ_NO_ACTION;
if(++suwPwmDelayOutCnt > 2)
{
EALLOW;
EPwm2Regs.TZCLR.bit.OST = 1;
EPwm3Regs.TZCLR.bit.OST = 1;
EDIS;
suwPwmDelayOutCnt = 1;
suwPwmDelayOutFlag = TRUE;
}
}
}
else
{
EPwm2Regs.AQCSFRC.bit.CSFA = AQ_CLEAR;
EPwm2Regs.AQCSFRC.bit.CSFB = AQ_CLEAR;
EPwm3Regs.AQCSFRC.bit.CSFA = AQ_CLEAR;
EPwm3Regs.AQCSFRC.bit.CSFB = AQ_CLEAR;
EALLOW;
EPwm2Regs.TZFRC.bit.OST = 1;
EPwm3Regs.TZFRC.bit.OST = 1;
EDIS;
suwPwmDelayOutCnt = 0;
suwPwmDelayOutFlag = FALSE;
}
}
void EPWM2_RegCongfig(void)
{
/*-----------------------------------ePWM3 Start-----------------------------------*/
EALLOW;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; //Force EPWMA to a low state
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; //Force EPWMB to a low state
EPwm2Regs.TZFRC.bit.OST = 1; //SetUp the software force OST bit
EPwm2Regs.ETCLR.bit.INT = 1; // Clears the INT flag bit
EPwm2Regs.ETCLR.bit.SOCA = 1; // Clears the SOCA flag bit
// TB module
EPwm2Regs.TBPRD = LLC_PWM_MIN_PERIOD; // Set timer period
EPwm2Regs.TBCTR = 0; // Clear counter, Time Base Counter Register
EPwm2Regs.TBPHS.bit.TBPHS = 0;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT/2
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Master module
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; // 0x1
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register when the time-base counter,TBCTR, is equal to zero could be design for immediately, need test
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //TB_SYNC_IN; // Sync down-stream module
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // symmetrical mode Count up and down
//bit15-14 11: FREE_SOFT, 00: Stop after the next time-base counter increment or decrement, 01: Stop when counter completes a whole cycle, 1x = Free run
//bit13 0: PHSDIR, 0 = count down after sync event, 1 = count up after sync event
//bit12-10 000: CLKDIV, 000= 2^0, 001= 2^1, ..., 111 = 2^7, TBCLK = EPWMCLK/(HSPCLKDIV*CLKDIV)
//bit9-7 001: HSPCLKDIV, Pre-scale, 000 = 1, 001 = 2, 010 = 4, ..., 110 = 12, 111 = 14.
//bit6 0: SWFSYNC, 0 = no software sync produced, 1 = writing a 1 forces a one-time sync pulse
//bit5-4 00: SYNCOSEL, sync-output-select, 00 = EPWMxSYNC, 01 =>CTR=0, 10 =>CTR=CMPB, 11 = sync-out disabled
//bit3 0: PRDLD, 0 = reload TBPRD on counter=0 from shadow, 1 = without shadow
//bit2 1: PHSEN, 0 = phase control disabled, master mode, 1 = slave mode
//bit1-0 10: CTRMODE, Counter Mode, 00 = Up, 01 = Down, 10 = Up-Down, 11 = Stop timer stopped (disabled)
// Counter Compare Control Register
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Compare A Register Shadow mode
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // Compare B Register Shadow mode
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on CTR = ZERO or PERIOD
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // Load on CTR = ZERO or PERIOD
//bit15-14 0: reserved
//bit13-12 00: LOADBSYNC: 00: according to LOADBMODE, 01:both according to LOADBMODE bits and when SYNC occurs, 10:Load only when a SYNC is received, 11:Reserved
//bit11-10 00: LOADASYNC: 00: according to LOADBMODE, 01:both according to LOADBMODE bits and when SYNC occurs, 10:Load only when a SYNC is received, 11:Reserved
//bit9 0: SHDWBFULL, read-only
//bit8 0: SHDWAFULL, read-only
//bit7 0: reserved
//bit6 0: SHDWBMODE, 0 = shadow mode, 1= immediate
//bit5 0: reserved
//bit4 0: SHDWAMODE, 0 = shadow mode, 1= immediate
//bit3-2 10: LOADBMODE, 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, disable
//bit1-0 10: LOADAMODE, 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, disable
//Dead-Band Generator Control register
EPwm2Regs.DBCTL.bit.IN_MODE = DBB_RED_DBA_FED;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high complementary (AHC). EPWMxB is inverted.
//bit15 0: HALFCYCLE: Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. 1: Half cycle clocking enabled.
//bit14 0: DEDB_MODE: Dead Band Dual-Edge B Mode Control
//bit13-12 0: OUTSWAP: Dead Band Output Swap Control
//bit11 0: SHDWDBFEDMODE: FED Dead-Band Load Mode 0 = immediate, 1= shadow mode
//bit10 0: SHDWDBREDMODE: RED Dead-Band Load Mode 0 = immediate, 1= shadow mode
//bit9-8 00: LOADFEDMODE: DBFED 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, disable
//bit7-6 00: LOADREDMODE: DBRED 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, disable
//bit5-4 00: IN_MODE, 00 = A->both, 01 = B->RED and A->FED, 10 = B->RED and B->FED, 11 = B->both
//bit3-2 10: POLSEL, polarity select for output, 00 = AH, 01 = ALC, 10 = AHC, 11 = AL
//bit1-0 11: OUT_MODE, 00 = no DB, 01 = No RED, 10 = No FED, 11 = DB fully enabled
EPwm2Regs.DBRED.bit.DBRED = LLC_MIN_DEAD_TIME; // 80 Dead time 1/90MHz*80= 0.9us//0.01667
EPwm2Regs.DBFED.bit.DBFED = LLC_MIN_DEAD_TIME; // Modify to 1.28us Joe 2018-04-08
// AQ module,
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // CNT=CMPA up ->0
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; // CNT=CMPA down->1
EPwm2Regs.AQCTLA.bit.PRD = AQ_NO_ACTION; // CNT=PRD no action
EPwm2Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION; // CNT=Zero SET
EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; // CNT=CMPA up ->1
EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR; // CNT=CMPA down->0
EPwm2Regs.AQCTLB.bit.PRD = AQ_NO_ACTION; // CNT=PRD no action
EPwm2Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION; // CNT=Zero SET
EPWM_enableGlobalLoadRegisters(EPWM2_BASE, EPWM_GL_REGISTER_CMPA_CMPAHR|
EPWM_GL_REGISTER_TBPRD_TBPRDHR|EPWM_GL_REGISTER_CMPB_CMPBHR|EPWM_GL_REGISTER_AQCSFRC); //根据需要添加
EPWM_setGlobalLoadTrigger(EPWM2_BASE, EPWM_GL_LOAD_PULSE_SYNC);
EPWM_enableGlobalLoadOneShotMode(EPWM2_BASE);
EPWM_enableGlobalLoad(EPWM2_BASE);
EPWM_setupEPWMLinks(EPWM2_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_GLDCTL2);
//Action-qualifier control register A/B
//bit15-12 0000: reserved
//bit11-10 00: CBD, 00 = do nothing, 01, clear, 10 = set, 11 = toggle
//bit9-8 00: CBU,
//bit7-6 10: CAD,
//bit5-4 01: CAU,
//bit3-2 00: PRD,
//bit1-0 00: ZRO,
// Action Qualifier Software Force Register
EPwm2Regs.AQSFRC.bit.RLDCSF = 0;
//bit15-8 reserved
//bit7-6 11: RLDCSF Active Register Reload From Shadow Options 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, immediately
//bit5 0: OTSFB One-Time Software Forced Event on Output B 0 = no effect, 1 = Initiates a single software forced event
//bit4-3 00: ACTSFB Action When One-Time Software Force B is Invoked 00 = disable, 01 = clear, 10 = set, 11 = toggle
//bit2 0: OTSFA One-Time Software Forced Event on Output A 0 = no effect, 1 = initial a single S/w force event
//bit1-0 00: ACTSFA Action When One-Time Software Force A Is Invoked 00 = disable, 01 = clear, 10 = set, 11 = toggle
//Action Qualifier Continuous S/W Force Register
EPwm2Regs.AQCSFRC.bit.CSFA = AQ_CLEAR;
EPwm2Regs.AQCSFRC.bit.CSFB = AQ_CLEAR;
//bit15-4 reserved
//bit3-2 01: CSFB, 00 = disable; 01 = contiguous low, 10 = contiguous high, 11 = no effect
//bit1-0 01: CSFA, 00 = disable; 01 = contiguous low, 10 = contiguous high, 11 = no effect
// Event Trigger Selection Register
EPwm2Regs.ETSEL.all = 0x0000;
EPwm2Regs.ETSEL.bit.INTEN = 0; // Disable INT
//EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
//EPwm2Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group //1; // Enable SOC on A group
//EPwm2Regs.ETSEL.bit.SOCASEL = ET_CTR_PRDZERO; // Select SOC from CMPA on upcount
//bit15 0: SOCBEN, Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0: Disable EPWMxSOCB 1: Enable EPWMxSOCB pulse
//bit14-12 000: SOCBSEL EPWMxSOCB Selection Options
//001 => TBCTR=0, 010 => TBCTR=TBPRD, 011 = TBCTR= TBPRD or 0
//100 = CMPA or CMPC inc, 101 = CMPA or CMPC dec, 110 = CMPB OR CMPD inc, 111 = CMPB OR CMPD dec.
//bit11 0: SOCAEN, 1 = enable SOCA, 0 = disable
//bit10-8 000: SOCASEL Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse same as SOCBSEL
//bit7 0: reserved
//bit6 0: INTSELCMP EPWMxINT Compare Register Selection Options 0: Enable Select CMPA/CMPB 1: Enable Select CMPC/CMPD
//bit5 0: SOCBSELCMP EPWMxSOCB Compare Register Selection Options 0: Enable Select CMPA/CMPB 1: Enable Select CMPC/CMPD
//bit4 0: SOCASELCMP EPWMxSOCA Compare Register Selection Options 0: Enable Select CMPA/CMPB 1: Enable Select CMPC/CMPD
//bit3 0: INTEN EPWMx_INT, 0 = disable interrupt, 1 = enable
//bit2-0 000: INTSEL same as SOCBSEL
// Event Trigger Pre-Scale Register
EPwm2Regs.ETPS.all = 0x0000;
//EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // generate interrupt on INTCNT=01(first event)
//EPwm2Regs.ETPS.bit.SOCAPRD = ET_1ST; // Generate pulse on SOCACNT=01(first event)
//bit15-14 00: SOCBCNT EPWMxSOCB Counter Register, read-only
//bit13-12 00: SOCBPRD EPWMxSOCB Period Select, 00 = disable, 01,10,11 = Generate EPWMxSOCB pulse on the 1/2/3 event.
//bit11-10 00: SOCACNT EPWMxSOCA Counter Register, read-only
//bit9-8 00: SOCAPRD EPWMxSOCA Period Select, 00 = disable, 01,10,11 = Generate EPWMxSOCA pulse on the 1/2/3 event.
//bit7-6 0000: reserved
//bit5 0: SOCPSSEL EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [INTCNT, and INTPRD] registers to determine frequency of events
//bit4 0: INTPSSEL EPWMxINTn Pre-Scale Selection Bits 1: Selects ETINTPS [ INTCNT2, and INTPRD2 ] registers to determine frequency of events (interrupt once every 0-15 events).
//bit3-2 00: INTCNT EPWMx_INT Counter Register
//bit1-0 00: INTPRD EPWMx_INT Period Select00 = disable, 01,10,11 = Generate EPWMxSOCA pulse on the 1/2/3 event.
/*-----------------------------------ePWM2 End-------------------------------------*/
EDIS;
}
void EPWM1_RegCongfig(void)
{
/*-----------------------------------ePWM1 Start-----------------------------------*/
EALLOW;
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; //Force EPWMA to a low state
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; //Force EPWMB to a low state
EPwm1Regs.TZFRC.bit.OST = 1; //SetUp the software force OST bit
EDIS;
EPwm1Regs.ETCLR.bit.INT = 1; // Clears the INT flag bit
EPwm1Regs.ETCLR.bit.SOCA = 1; // Clears the SOCA flag bit
// TB module
EPwm1Regs.TBPRD = LLC_PWM_MIN_PERIOD; // Set timer period
EPwm1Regs.TBCTR = 0; // Clear counter, Time Base Counter Register
EPwm1Regs.TBPHS.all = 0; // Set Phase register to zero
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; // 0x1
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; //The period register (TBPRD) is loaded from its shadow register when the time-base counter,TBCTR, is equal to zero could be design for immediately, need test
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //TB_SYNC_IN; // Sync down-stream module
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // symmetrical mode Count up and down
//bit15-14 11: FREE_SOFT, 00: Stop after the next time-base counter increment or decrement, 01: Stop when counter completes a whole cycle, 1x = Free run
//bit13 0: PHSDIR, 0 = count down after sync event, 1 = count up after sync event
//bit12-10 000: CLKDIV, 000= 2^0, 001= 2^1, ..., 111 = 2^7, TBCLK = EPWMCLK/(HSPCLKDIV*CLKDIV)
//bit9-7 001: HSPCLKDIV, Pre-scale, 000 = 1, 001 = 2, 010 = 4, ..., 110 = 12, 111 = 14.
//bit6 0: SWFSYNC, 0 = no software sync produced, 1 = writing a 1 forces a one-time sync pulse
//bit5-4 00: SYNCOSEL, sync-output-select, 00 = EPWMxSYNC, 01 =>CTR=0, 10 =>CTR=CMPB, 11 = sync-out disabled
//bit3 0: PRDLD, 0 = reload TBPRD on counter=0 from shadow, 1 = without shadow
//bit2 1: PHSEN, 0 = phase control disabled, master mode, 1 = slave mode
//bit1-0 10: CTRMODE, Counter Mode, 00 = Up, 01 = Down, 10 = Up-Down, 11 = Stop timer stopped (disabled)
// Counter Compare Control Register
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Compare A Register Shadow mode
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // Compare B Register Shadow mode
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on CTR = ZERO or PERIOD
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // Load on CTR = ZERO or PERIOD
//bit15-14 0: reserved
//bit13-12 00: LOADBSYNC: 00: according to LOADBMODE, 01:both according to LOADBMODE bits and when SYNC occurs, 10:Load only when a SYNC is received, 11:Reserved
//bit11-10 00: LOADASYNC: 00: according to LOADBMODE, 01:both according to LOADBMODE bits and when SYNC occurs, 10:Load only when a SYNC is received, 11:Reserved
//bit9 0: SHDWBFULL, read-only
//bit8 0: SHDWAFULL, read-only
//bit7 0: reserved
//bit6 0: SHDWBMODE, 0 = shadow mode, 1= immediate
//bit5 0: reserved
//bit4 0: SHDWAMODE, 0 = shadow mode, 1= immediate
//bit3-2 10: LOADBMODE, 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, disable
//bit1-0 10: LOADAMODE, 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, disable
//Dead-Band Generator Control register
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high complementary (AHC). EPWMxB is inverted.
//bit15 0: HALFCYCLE: Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. 1: Half cycle clocking enabled.
//bit14 0: DEDB_MODE: Dead Band Dual-Edge B Mode Control
//bit13-12 0: OUTSWAP: Dead Band Output Swap Control
//bit11 0: SHDWDBFEDMODE: FED Dead-Band Load Mode 0 = immediate, 1= shadow mode
//bit10 0: SHDWDBREDMODE: RED Dead-Band Load Mode 0 = immediate, 1= shadow mode
//bit9-8 00: LOADFEDMODE: DBFED 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, disable
//bit7-6 00: LOADREDMODE: DBRED 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, disable
//bit5-4 00: IN_MODE, 00 = A->both, 01 = B->RED and A->FED, 10 = B->RED and B->FED, 11 = B->both
//bit3-2 10: POLSEL, polarity select for output, 00 = AH, 01 = ALC, 10 = AHC, 11 = AL
//bit1-0 11: OUT_MODE, 00 = no DB, 01 = No RED, 10 = No FED, 11 = DB fully enabled
EPwm1Regs.DBRED.bit.DBRED = BB_DEAD_TIME; // 80 Dead time 1/90MHz*80= 0.9us//0.01667
EPwm1Regs.DBFED.bit.DBFED = BB_DEAD_TIME; // Modify to 1.28us Joe 2018-04-08
// AQ module,
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // CNT=CMPA up ->1
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // CNT=CMPA down->0
EPwm1Regs.AQCTLA.bit.PRD = AQ_NO_ACTION; // CNT=PRD no action
EPwm1Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION; // CNT=Zero SET
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; // CNT=CMPA up ->1
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // CNT=CMPA down->0
EPwm1Regs.AQCTLB.bit.PRD = AQ_NO_ACTION; // CNT=PRD no action
EPwm1Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION; // CNT=Zero SET
//Action-qualifier control register A/B
//bit15-12 0000: reserved
//bit11-10 00: CBD, 00 = do nothing, 01, clear, 10 = set, 11 = toggle
//bit9-8 00: CBU,
//bit7-6 10: CAD,
//bit5-4 01: CAU,
//bit3-2 00: PRD,
//bit1-0 00: ZRO,
EPWM_enableGlobalLoadRegisters(EPWM1_BASE, EPWM_GL_REGISTER_CMPA_CMPAHR|
EPWM_GL_REGISTER_TBPRD_TBPRDHR|EPWM_GL_REGISTER_CMPB_CMPBHR|EPWM_GL_REGISTER_AQCSFRC); //根据需要添加
EPWM_setGlobalLoadTrigger(EPWM1_BASE, EPWM_GL_LOAD_PULSE_CNTR_ZERO);
EPWM_enableGlobalLoadOneShotMode(EPWM1_BASE);
EPWM_enableGlobalLoad(EPWM1_BASE);
// Action Qualifier Software Force Register
EPwm1Regs.AQSFRC.bit.RLDCSF = 0;
//bit15-8 reserved
//bit7-6 11: RLDCSF Active Register Reload From Shadow Options 00 => CTR=0; 01 =>CTR=PRD, 10 => CTR=0 or CTR=PRD, 11, immediately
//bit5 0: OTSFB One-Time Software Forced Event on Output B 0 = no effect, 1 = Initiates a single software forced event
//bit4-3 00: ACTSFB Action When One-Time Software Force B is Invoked 00 = disable, 01 = clear, 10 = set, 11 = toggle
//bit2 0: OTSFA One-Time Software Forced Event on Output A 0 = no effect, 1 = initial a single S/w force event
//bit1-0 00: ACTSFA Action When One-Time Software Force A Is Invoked 00 = disable, 01 = clear, 10 = set, 11 = toggle
//Action Qualifier Continuous S/W Force Register
EPwm1Regs.AQCSFRC.bit.CSFA = AQ_CLEAR;
EPwm1Regs.AQCSFRC.bit.CSFB = AQ_CLEAR;
//bit15-4 reserved
//bit3-2 01: CSFB, 00 = disable; 01 = contiguous low, 10 = contiguous high, 11 = no effect
//bit1-0 01: CSFA, 00 = disable; 01 = contiguous low, 10 = contiguous high, 11 = no effect
// Event Trigger Selection Register
EPwm1Regs.ETSEL.all = 0x0000;
EPwm1Regs.ETSEL.bit.INTEN = 0; // Enable INT
// EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group //from tl-xh dsp by lzy
// EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_PRDZERO; // Select SOC from CMPA on upcount //from tl-xh dsp by lzy
//bit15 0: SOCBEN, Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0: Disable EPWMxSOCB 1: Enable EPWMxSOCB pulse
//bit14-12 000: SOCBSEL EPWMxSOCB Selection Options
//001 => TBCTR=0, 010 => TBCTR=TBPRD, 011 = TBCTR= TBPRD or 0
//100 = CMPA or CMPC inc, 101 = CMPA or CMPC dec, 110 = CMPB OR CMPD inc, 111 = CMPB OR CMPD dec.
//bit11 0: SOCAEN, 1 = enable SOCA, 0 = disable
//bit10-8 000: SOCASEL Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse same as SOCBSEL
//bit7 0: reserved
//bit6 0: INTSELCMP EPWMxINT Compare Register Selection Options 0: Enable Select CMPA/CMPB 1: Enable Select CMPC/CMPD
//bit5 0: SOCBSELCMP EPWMxSOCB Compare Register Selection Options 0: Enable Select CMPA/CMPB 1: Enable Select CMPC/CMPD
//bit4 0: SOCASELCMP EPWMxSOCA Compare Register Selection Options 0: Enable Select CMPA/CMPB 1: Enable Select CMPC/CMPD
//bit3 0: INTEN EPWMx_INT, 0 = disable interrupt, 1 = enable
//bit2-0 000: INTSEL same as SOCBSEL
// Event Trigger Pre-Scale Register
EPwm1Regs.ETPS.all = 0x0000;
//EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // generate interrupt on INTCNT=01(first event)
//EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST; // Generate pulse on SOCACNT=01(first event)
//bit15-14 00: SOCBCNT EPWMxSOCB Counter Register, read-only
//bit13-12 00: SOCBPRD EPWMxSOCB Period Select, 00 = disable, 01,10,11 = Generate EPWMxSOCB pulse on the 1/2/3 event.
//bit11-10 00: SOCACNT EPWMxSOCA Counter Register, read-only
//bit9-8 00: SOCAPRD EPWMxSOCA Period Select, 00 = disable, 01,10,11 = Generate EPWMxSOCA pulse on the 1/2/3 event.
//bit7-6 0000: reserved
//bit5 0: SOCPSSEL EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [INTCNT, and INTPRD] registers to determine frequency of events
//bit4 0: INTPSSEL EPWMxINTn Pre-Scale Selection Bits 1: Selects ETINTPS [ INTCNT2, and INTPRD2 ] registers to determine frequency of events (interrupt once every 0-15 events).
//bit3-2 00: INTCNT EPWMx_INT Counter Register
//bit1-0 00: INTPRD EPWMx_INT Period Select00 = disable, 01,10,11 = Generate EPWMxSOCA pulse on the 1/2/3 event.
/*-----------------------------------ePWM3 End-------------------------------------*/
}
BR
Emma
