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TMS320F28388D: eQEP module index detection

Part Number: TMS320F28388D

Hello,

I am using eQEP module on TMS320F28388D. My source of signal generates index signal gated to A and B as shown on figure 27-3 in reference manual (SPRUII0B).

 

I have following initialization sequence:

    Set GPIO multiplexor to QEP module

    Init GPIOs as synchronous input,

    QDECCTL[XCR] = 1

    QDECCTL[QIDIRE] = 1

    QEPCTL[FREE_SOFT] = 2

    QPOSMAX = 4095

    QPOSINIT = initialPosition // Obtained from source via serial communication

    QEPCTL[SWI] = 1

    QEPCTL[QPEN] = 1

I have problem with detecting of index signal by the CPU.

  • Sometimes, it works OK.
  • Sometimes, index pulse is detected one step away:
    • QEPSTS[PCEF] is set to 1
    • QPOSILAT is equal to 1 instead of 0, or 4094 instead of 4095 (depend on direction of movement)
    • By next shaft turn error is usually cleared
    • When I change direction of movement, index error sometimes appears again, sometimes not.
    • I noticed that QEPSTS[FIMF], which should be set when first index is received is NEVER set to 1.
  • To make things more complicated, I have two CPUs connected to one source of QEP signal, but they are not acting the same. Sometimes firs one acting problematically, sometimes second one, sometimes both, sometimes both are OK.
    • Also sometimes, when I am spinning by shaft for example to the right, one of CPU detect transition of index signal by turning right, and second one detects transition to the left (QEPSTS[QDLF]).

At first, I used QDECCTL[QIDIRE] = 0

  • Issue happened more often
  • Difference was not just 1, but usually 2 or 3.
  • QEPSTS[FIMF], which should be set when first index is received is sometimes set to 1, sometimes not, again one CPU have the flag set, one not and so on.

When I am looking on QEP signals on logic analyzer, timing of signals looks good.

So, please:

  1. Do you see any problem in QEP configuration?
  2. Can you please advise me what else I can do to make detection of the index signal working correctly?
  3. Is there available any documentation of QDECCTL[QIDIRE] bit functionality? I did not found anything describing what it is good for, what it should solve, …
  • Hi, 

    Let me get back to you on the XDIRE functionality in next couple of days. What is the value of PCRM?

    May I know what is the used case of running same eQEP from both the CPUs? I am not sure how the arbitration happens on the Peripheral bus when both the CPUs try to access the same address, to avoid that you can use IPC, not sure if you are already doing that?

    Best Regards,

    Nirav

  • Hello,

    - Value of PCRM is its default value = 0 (Position counter reset on an index event)

    - I am sorry, I did not wrote it clearly. By CPU, I mean physical TMS320F28388D devices. So I have two TMS320F28388D connected to one QEP signal sources. CPU1 in each TMS320F28388D is used.

  • Thanks for the information Martin. Let me get back to you in next couple of days.

    Best Regards,

    Nirav

  • Hi Martin,

    Apologies for the delayed response, we had some internal restructuring and I am now assigned to help you on this inquiry.

    1. To further assist me, do you have any scope outputs you can provide to help me visualize this? 

    2. Can you check the eQEP inputs for potential noise? It seems like the issues occur sporadically which leads me to believe there may be some noise affecting the signals.

    3. You mentioned that index is gated to A and B signals, can you verify again if these signals are synchronized?

    Regards,

    Peter