This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello,
I am using eQEP module on TMS320F28388D. My source of signal generates index signal gated to A and B as shown on figure 27-3 in reference manual (SPRUII0B).
I have following initialization sequence:
Set GPIO multiplexor to QEP module
Init GPIOs as synchronous input,
QDECCTL[XCR] = 1
QDECCTL[QIDIRE] = 1
QEPCTL[FREE_SOFT] = 2
QPOSMAX = 4095
QPOSINIT = initialPosition // Obtained from source via serial communication
QEPCTL[SWI] = 1
QEPCTL[QPEN] = 1
I have problem with detecting of index signal by the CPU.
At first, I used QDECCTL[QIDIRE] = 0
When I am looking on QEP signals on logic analyzer, timing of signals looks good.
So, please:
Hi,
Let me get back to you on the XDIRE functionality in next couple of days. What is the value of PCRM?
May I know what is the used case of running same eQEP from both the CPUs? I am not sure how the arbitration happens on the Peripheral bus when both the CPUs try to access the same address, to avoid that you can use IPC, not sure if you are already doing that?
Best Regards,
Nirav
Hello,
- Value of PCRM is its default value = 0 (Position counter reset on an index event)
- I am sorry, I did not wrote it clearly. By CPU, I mean physical TMS320F28388D devices. So I have two TMS320F28388D connected to one QEP signal sources. CPU1 in each TMS320F28388D is used.
Thanks for the information Martin. Let me get back to you in next couple of days.
Best Regards,
Nirav
Hi Martin,
Apologies for the delayed response, we had some internal restructuring and I am now assigned to help you on this inquiry.
1. To further assist me, do you have any scope outputs you can provide to help me visualize this?
2. Can you check the eQEP inputs for potential noise? It seems like the issues occur sporadically which leads me to believe there may be some noise affecting the signals.
3. You mentioned that index is gated to A and B signals, can you verify again if these signals are synchronized?
Regards,
Peter