Hi Team, seeking for your assistance.
Setting EPWMCLKDIV bit to 0 it s possible to use the full 200MHz system clock as a source for the TBCLK of EPWM. This is also verified with the datasheet electrical specification stating 200MHz as the maximum EPWM clock.
Since all examples in the Technical Reference Manual related to the High Resolution mode are given with 100MHz EPWM clock my question is would this mode be working also with 200MHz input clock?
If the MEP scaling for 100MHz clock is 66-67 to obtain 150ps which is the typical MEP step from the datasheet electrical specification, for 200MHz clock the MEP scaling will be twice smaller value as the PWM clock is now 5ns instead of 10ns.
Would the Resolution mode work?
Would the auto-conversion functionality work (AUTOCONV bit set to 1).
Would the SFO calibration software work?
Thank you
