We designed a control scheme in which the control algorithm and supervisory checks (over current, voltage, temperature etc) were performed on the same ISR. Basically the gates switching PWM @20 KHz triggers ADC Start Of Conversions. The End Of Conversions EOC of the last control measurements triggers the control ISR. Since hardware tripping circuit was not incorporated for all relevant signals so there is an idea to perform supervisory checks in a relatively much faster ISR. This idea is shown in the diagram below:
I understand that we might have to enable two interrupts, a high priority supervisory interrupt executing @ 100 KHz (using a 100 KHz PWM synchronized with the 10 KHz PWM) and a lower priority control interrupt executing at 20 KHz (triggered with gate switching PWM). In this regard I have the following queries:
1- Is this a good approach considering that hardware trips are not implemented for some fast rising voltages/currents in the hardware?. Is there a better and more efficient way?.
2- Do I need to configure separate SOCs for the control ISR and supervisory ISR although both will be sampling the same control inputs?. Is there a more efficient and better way to trigger both ISRs for e.g. both ISRs can use common ADC conversion at some instances when their execution times overlap.
3- How to set priorities for both ISRs?. I understand that supervisory ISR can be assigned to ADCA1 interrupt i.e. highest priority interrupt. Should we assign other ADC interrupt such as ADCB1 for the control ISR?. Also I think that software method might be required for nesting interrupts so that supervisory ISR can interrupt the control ISR.
