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TMS320F28377D: Behavior of EMIF data lines

O.H
Mastermind 7210 points

Part Number: TMS320F28377D

Hi experts,

Please let me confirm the behavior of EMIF.

Q: Is it normal behavior for the data line to go Low level after read in the case shown in the figure-H below?
 
My customer is The FPGA is connected to the CPU's external bus (EMIF1_CS2n) and the FPGA's internal RAM is read/write (used as asynchronous memory). The bus is pulled up with 10kΩ and only the CPU and FPGA are connected.
 
The figure below shows the waveforms when data is written to and read from the FPGA.

  • Yellow: /WE signal of CPU
  • Red: /OE signal of CPU
  • Blue: Data bus D0
  • Green: Output Enable inside FPGA (external output for measurement)

Figure-H: High is written to data bus D0 and read back.

Figure-L: Low is written to data bus D0 and read back.

Here, in the figure-H, data bus D0 is at a High level until a High is written to it and read back, but after the reading is finished, it is at a Low level. They think the high section is due to TRM's "25.5.7 Data Bus Parking", but it goes low after the read. Since the FPGA is set to High-Z output except during read, they are assuming that the CPU is driving it to Low level, but they are wondering if this is normal behavior or if they are setting it wrong in some way. It is possible that the FPGA side is at fault, but they were just checking to see if the F28377D side is behaving as expected.

If there is any information missing, please let me know.

Best regards,
O.H

  • 0
    TI__Genius 10845 points

    Hi,

    This query has been assigned to the EMIF expert. Since he is OOO this week, please expect delay in response.

    Thanks
    Vasudha

  • 0
    TI__Guru** 117311 points

    Hi,

    Yes, EMIF drives the data lines all the time except when read is issued. As per definition, figure-H should have driven the data line high. I'll try to get more detail on this and I'll also suggest to check the logic of FPGA if it's continue to drive the data bus after read operation. 

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Mastermind 7210 points

    Hi Vasudha, Vivek Singh,

    Thank you for your reply.

    Vivek Singh said:
    Yes, EMIF drives the data lines all the time except when read is issued. As per definition, figure-H should have driven the data line high. I'll try to get more detail on this and I'll also suggest to check the logic of FPGA if it's continue to drive the data bus after read operation. 

    I understood that with the current information, it should be in a High state after the readout. We will ask our clients to confirm the FPGA, but would welcome any additional information from you.

    Best regards,
    O.H

  • 0 in reply to Vivek Singh
    Mastermind 7210 points

    Hi Vivek Singh,

    We received additional confirmation results from the customer.

    They rechecked the circuit and changed the signal to be measured. Their circuit was as follows:

     

    The bus connection between the CPU and FPGA was not directly connected, but through a 22Ω resistor. The data bus signal D0 reported in the previous article is the signal connected to the FPGA side. This time, D0 (CPU) connected to the CPU side is also measured at the same time. Although the /WE signal is not measured, the operation is the same as last time (write high and read back).

    Looking at this waveform, D0 (CPU0) on the CPU side and D0 on the FPGA side have the same waveform. If the CPU is driven High and the FPGA is driven Low after read, then D0 (CPU) would be at 3.3V (or intermediate potential). Therefore, the CPU is considered to be driving Low, not High.

    Note that this waveform also occurs when the CPU is a High-Z output and the FPGA is a Low output. However, in that case, when the CPU writes High, the High output of the CPU and the Low output of the FPGA should collide and an intermediate potential should be observed. However, the waveform that changes from Low to High at once is actually observed. It seems that no collision has occurred. Therefore, we consider it unlikely that the FPGA is outputting Low.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru** 117311 points

    Thank you for the confirmation. Let me get some more detail on bus parking feature and I'll get back to you in 1-2 days.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Mastermind 7210 points

    Hi Vivek Singh,

    Sorry for rush you. Is there any update?

    My customers are looking for a response, so it would be helpful to know the status.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru** 117311 points

    Hi,

    I am waiting for our design team response on this. I'll ping them again today. 

    Regards,

    Vivek Singh

  • +1 in reply to O.H
    TI__Guru** 117311 points

    HI,

    We checked the simulation and confirm that customer observation is correct. After read operation, data lines are driven low. We'll work on updating our document with this finding. I hope customer will be able to work this out.

    Let me know if any further query on this.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Mastermind 7210 points

    Hi,

    Thank you for your support. I understood.

    If I have any additional questions I will contact you again.

    Best regards,
    O.H

  • +1 in reply to O.H
    TI__Guru** 117311 points

    Sure. We can close this post and re-open it or start new post for any additional query.

    Regards,

    Vivek Singh