TMS320F28388D: C28 CPU1 access as 16-bit size when EMIF1 is 32-bit data bus ?

Hi,

This query has been assigned to the EMIF expert. Since he is OOO this week, please expect delay in response.

Thanks
Vasudha

Hi,

Hidehiko Kaya said:

A software on CPU1 can access EMIF1 as a 16-bit word address ?

Yes, CPU can perform 16bit data access to 32bit memory device.

Hidehiko Kaya said:

DSP has 16-bit data on 1 address, so CGT can output assemble (16-bit access x2 ) as a 32-bit access.

Not clear on this query. Can you please provide more detail on this ?

Hidehiko Kaya said:

EM1BA[1] can work the LSB as 16-bit word access when EMIF1 is 32-bit mode.

BA is bank address so it has nothing to do with 16bit access. It's EM1DQM signals which is used to get valid 16bit data from 32bit for 16bit operation.

Hidehiko Kaya said:

EM1BA[1] can work the LSB as 16-bit word access when EMIF1 is 32-bit mode.

Same as point #1 and answer is "Yes".

Hidehiko Kaya said:

Could you please let us know when EMIF1 is 32-bit interface ?

As long as you have made proper connection of EM1DQM signal to external memory device, 16bit access should work fine. 

Regards,

Vivek Singh

Hi Vivek,

Thank you for your information.

I understand.

>>DSP has 16-bit data on 1 address, so CGT can output assemble (16-bit access x2 ) as a 32-bit access.

>Not clear on this query. Can you please provide more detail on this ?

We define struct type with bit field like below.

typedef struct{
....
	union{	/* FSCOM0_CONTROL_UN */
		UINT32 Word_u32;	/* UINT32 Access */
		struct{	/* Bit Access */
			UINT32 COM_EN : 1;	/* BIT0 */
			UINT32 ERROUT_EN : 1;	/* BIT1 */
			UINT32 Reserved : 7;
			UINT32 ERROR_EXTERNAL : 1;	/* BIT9 */
			UINT32 ERROR_HSCOM : 1;		/* BIT10 */
			UINT32 ERROR_INTERNAL : 1;	/* BIT11 */
			UINT32 Reserved2 : 20;
		}BIT_ST;
	}FSCOM0_CONTROL_UN;
.....	
}AX7_FSCOM0_ST;

We implement to access a bit field, then CGT creates  16-bit word x2 assemble code.

AX7_fscom0_stg.FSCOM0_CONTROL_UN.BIT_ST.COM_EN = 1UL;

CGT output assemble code like below.

00000003 9802 OR @0x2, AL
00000004 9903 OR @0x3, AH

In this case, we need only 32-bit data access because cost of FPGA logic is lower than both 16 and 32-bit address.

However we avoid this problem and give up bit-field in structure. 

Best regards,

Hidehiko

Yes, compiler can always generate 2 16bit operation instead of 32bit. Best option is to fix board to allow 32 as well as 16bit access.

Regards,

Vivek Singh

Hi Vivek,

When we donot apply bit field in structure, CGT always generates 32-bit operation.

Therefore when we apply EMIF1 -32bit, we always define structure type without bit field.

If you know a way to avoid "CGT generates 2 16bit operation instead of 32bit", could you let us know ?

Best regards,

Hidehiko  

HI,

Hidehiko Kaya said:

If you know a way to avoid "CGT generates 2 16bit operation instead of 32bit", could you let us know ?

I am looping our compiler team to provide detail on this.

Regards,

Vivek Singh