Hi,
I'm designing a system where SPI transactions are executed via DMA and triggered by EPWM10SOCA event (configured here as rising edge of PWM10 signal). I noticed 2 things on the SPI transactions:
- The SPI transaction doesn't work right away, there is a "long" delay between the SOCA event and the 1st SPI clock cycle (delay of ~1µs, which represents 100 system clock cycles since CPU is running at 100MHz)
- There is a +/-0.2µs jitter on the exact moment the SPI clock is starting compared to PWM10 rising edge. So total delay is between 0.8µs and 1.2µs depending on cycle.
Where does the delay comes from? And can I control the jitter (so having my start of SPI clock synchronized with my PWM)?
I already tried to remove any delay in the DMA by having the source address and the destination both being in the SPI peripheral register range, but this didn't change anything. My configuration is the following:
- CPU running at 100MHz
- SPI is configured for 2.5MHz clock
- PWM10 is a 7.5kHz square signal (EPWM in counting up mode, CMPA = period / 2)
- PWM10 triggers SOCA event:
EPWM_setADCTriggerSource(EPWM10_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO); EPWM_setADCTriggerEventPrescale(EPWM10_BASE, EPWM_SOC_A, 1); EPWM_enableADCTrigger(EPWM10_BASE, EPWM_SOC_A);
- DMA is triggered by SOCA event and fills the SPI Tx buffer:
DMA_configAddresses(DMA_CH5_BASE, (uint16_t *)(SPIB_BASE + SPI_O_TXBUF), srcAddr); DMA_configMode(DMA_CH5_BASE, DMA_TRIGGER_EPWM10SOCA, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
Best regards,
Stephane
