TMS320F280049: ePWM AQ module Software forced event AQCSFRC.bit.CSFA and AQCSFRC.bit.CSFB are invalid

Yale Li 李耀先

Expert 4660 points

Part Number: TMS320F280049

Hi Team,

Here's an issue form the customer may need your help:

The figure below shows the configuration of customer's ePWM3 module.

ePWM_config

They are configured as follows before configuring the ePWM module:

CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

After configuring the ePWM module, perform the following configuration:

CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

ePWM3A and ePWM3B output low level through the following code during initialization:

EPwm3Regs.AQSFRC.bit.RLDCSF = 1; /* Load when counter=PRD */
EPwm3Regs.AQCSFRC.bit.CSFA = SWFOR_CLEAR;
EPwm3Regs.AQCSFRC.bit.CSFB = SWFOR_SET;

However, during the actual test, it was found that ePWM3A is low level, ePWM3B is always high level, and the output level change cannot be achieved by continuing to operate CSFA and CSFB in the following application program.

At this time, if change the 2 shown in below figure from

EPwm3Regs.AQSFRC.bit.RLDCSF = 1; /* Load when counter=PRD */

EPwm3Regs.AQSFRC.bit.RLDCSF = 3; /* Load immediately */

Then the initial level of EPWM3A and EPWM3B can both be low level.

If keep

EPwm3Regs.AQSFRC.bit.RLDCSF = 1;

It is also normal to change TBPHS or TBCTR at 1 on the figure to 0, or change PHSEN at 3 to 0.

What causes such a problem? The customer thinks that it is a clock-related problem that causes the SW forced event to fail.

Thanks & Regards

Yale Li

over 4 years ago

0 Nima Eskandari over 4 years ago

TI__Guru 52220 points

The deadband module comes after the AQ module so it will always take affect after.

The load in shadow mode will only occur when CTR=0 and the TBCLK is enabled. So when you switch to immediate mode, you skip the load and make it happen immediately.

0 Yale Li 李耀先 over 4 years ago in reply to Nima Eskandari

TI__Expert 4660 points

Hi Nima,

Thanks for your support!

Load in shadow mode should not only happen when CTR=0, right? According to the description of EPwm3Regs.AQSFRC.bit.RLDCSF, it can be configured to load when CTR=0 or CTR=PDR.

The initial configuration of the customer is load when CTR=PRD, and TBCLK is disabled during configuration, so EPWM3A and 3B do not operate.
After the configuration is completed, TBCLK will be enabled, so when CTR counts to PRD, EPWM3A and EPWM3B should both go low. But EPWM3A is always low and EPWM3B is always high. Output level change is also not possible by manipulating CSFA and CSFB.

May I ask what is the reason?

Thanks & Regards

Yale Li