LAUNCHXL-F280049C: EPWM ADC SOCA trigger counts fail.

Hi,

Sorry for the delayed response. I have forwarded your query to the expert. Request your patience.

Regards,

Aditya

Sorry I couldnt find a clear question. You SOCA is not triggering on CMPD?

Hi Nema

The question is obvious match counts CMPD used to trigger the ADC via SOCA are not actually working based on source CNT=PRD or source CMPD.

It does not seem to trigger ADC at least in the correct periodic time of CMPD 50µs match counts.  Even fails triggering SOCA set for 250µs via source Timebase Submodule (CNT=PRD) when (TBCTR=50µs) periods. The SOCA trigger periodic timing is not being constrained by the driver lib functions below. Setting CMPD match counts  >5 has no effect on the EOC registered ISR time. Also setting CMPD compare 2500 match count but ADC trigger source SOCA periodic ISR decimation time never expands up to 250µs, it remains a 25µs pulse period. 

Why does the periodic trigger time SOCA to ISR not change with the match count values?

// set EPWM1 trigger pulse, TBCTR=50µs*5 250µs or 25µs*1 CMPD-D
// setup the Event Trigger Selection Register (ETSEL)
EPWM_setADCTriggerSource(obj->pwmHandle[0], EPWM_SOC_A, EPWM_SOC_TBCTR_D_CMPD); // EPWM_SOC_TBCTR_PERIOD

// write value for ADC trigger (20KHz SOC_Int*5TBCTR=250µs, 1period=50µs)
EPWM_setCounterCompareValue(obj->pwmHandle[0], EPWM_COUNTER_COMPARE_D, 5)

Can you take the ADC Trigger signal out to a GPIO to see if it is in fact triggering or not?

Nima Eskandari said:

Can you take the ADC Trigger signal out to a GPIO to see if it is in fact triggering or not?

The ADC ISR has a GPIO trace that confirms SOCA being trigger but not at the frequency configured below. The ADC clock is 50MHz and EPWM module 100MHz. The SOCA trigger period should be derived from EPWM period (20KHz) or TBPRD 25µs up, 25µs down via CMPA. 

Setting CMPD below 25 to 2500 match count does not change the ADC trigger ISR decimation and SOCA remains runtime 25µs. CCS debug register view verifies CMPD has a match count but the trigger period SOCA is not associated with CMPD, rather seems to trigger via CMPA.  

// write value for ADC trigger (20KHz SOC_Int*5TBCTR=250µs, 1period=50µs)
EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_D, 2500)

Perhaps shadow load CMPD call is not working with for loop [cnt] loading of 3 generators?

// set the CMPD shadow load on period 
EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
EPWM_COUNTER_COMPARE_D,
EPWM_COMP_LOAD_ON_CNTR_PERIOD); //EPWM_COMP_LOAD_ON_CNTR_ZERO  

The other problem is the motor control SDK hal.c configured CMPD as the ADC trigger source. Later below code snip call from SOCA triggered ISR sets CMPC the SOCA trigger source count 1. That SOCA trigger change CMPC defies Instaspin decimation constraint define USER_NUM_PWM_TICKS_PER_ISR_TICK 3. 

// initialize PWM handles for Motor 1
obj->pwmHandle[0] = EPWM1_BASE;

EPWM_setInterruptEventCount(obj->pwmHandle[0], 3);
EPWM_setADCTriggerEventPrescale(obj->pwmHandle[0], EPWM_SOC_A, 3);

Can you try to set this up using SysConfig to see if the generated code is different than yours. I think it should be a minor coding error.

For the motor control HAL.c file please start a new thread and mention you are using the MCSDK.

Nima Eskandari said:

For the motor control HAL.c file please start a new thread and mention you are using the MCSDK.

Obviously, the hardware has issues with driver library shadow calls.  The SDK project is not the issue rather systemic fallout due to driverlib calls. The above calls are not functional with SOCA triggering ADC and EPWM interrupt counts. Code is failing to throttle EOC via SOCA interrupts for ADC triggered intervals.

Nima Eskandari said:

Can you try to set this up using SysConfig to see if the generated code is different than yours.

How will that prove if the driverlib calls (below) are even valid for the hardware triggering configuration?

The time between PWM interrupt counts and triggering ADC constrained by the set number of TBPRD periods is failing to link SOCA events to EPWM generator interrupt counts. That might be hardware issue or is simply a EPWM violation of driverlib calls that are not in the same control scope of SOCA triggered counts via Time Base, Actions Qualifier Submodules.

The driverlib method (below) is used to accumulate EPWM interrupt intervals for SOCA triggering of ADC is disabled in all PWM generators. That said how is that EPWM interrupts can be counted when they are disabled, never configured and never re-enabled? Is that even what the driver lib calls are supposed to do or something else entirely? I suspect it is a coding violation that EPWM Action Qualifier Submodule cannot count disabled interrupts. Yet the Event-Trigger Submodule generates EPWMxINT interrupts or counts SOCA events via CMPD. 

/* Clear the the EPWM trigger interrupts */
EPWM_disableInterrupt( EPWM1_BASE);
EPWM_disableInterrupt( EPWM2_BASE);
EPWM_disableInterrupt( EPWM4_BASE);

EPWM_setInterruptEventCount( EPWM1_BASE, 3);
EPWM_setADCTriggerEventPrescale(EPWM1_BASE, 3);

Seemingly the interrupt count for triggered ADC via TBPRD or CMPD is discussed in Event Trigger Submodule, TRM 18.10, Figures:18-45, 18-46, 18-47. The ETFRC[INT] bit will increment the INT[CNT] and needs to be cleared when INTCNT=INTPRD (250µs). Below are driverlib functions (epwm.h) clear INT[CNT] and ADC trigger flag register. I had once added these to ISR clear ACK group near the end of generated ISR but it did not increment the count.

/* clear EPWM1 Event Trigger Register Flag (ETCLR) */
EPWM_clearEventTriggerInterruptFlag(EPWM1_BASE);
EPWM_clearADCTriggerFlag(EPWM1_BASE, EPWM_SOC_A);

The SOCA event trigger interrupt driver (Fig.18-46) is somewhat complicated being EPWM interrupts were disabled. And SOCA count driver mode (Fig.18-47) produces 300µs triggered conversions via call below. Though Fig.18-46 labeling (ETCN) seems odd given the actual driverlib calls (posted above) and debug register bits being set for interrupt triggering.

How was the interrupt EPWMxINT ETFLG[INT] (Fig.18-46) cleared or ADC triggered without enabled EPWM interrupts, given driverlib calls first posted above?

If interrupts are disabled, ETSEL[INTEN] = 0, or the interrupt flag is set, ETFLG[INT] = 1, the counter stops counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD

 /* set the ADC trigger event counts */
EPWM_setADCTriggerEventCountInitValue(EPWM1_BASE, EPWM_SOC_A, 6);

So is your SOCASELCMP. If that is not set to 1 then how can CMPD propagate through?

Nima Eskandari said:

Your INTSELCMP is 0, it is using CMPB instead of CMPD.

Interrupts are disabled as count mode was configured. That was sort of the point that interrupt mode had disabled EPWM interrupts. Yet CMPD is configured and triggering ADC conversions but I see your point why is the register 0x0?

Nima Eskandari said:

If that is not set to 1 then how can CMPD propagate through?

ETSEL(SOCASELCMP) is enabled CMPD in down count mode 0x111. It didn't make sense to me configuration used interrupt trigger mode with disable EPWM interrupts. There are driverlib comments interrupt mode EPWMnINT can only trigger 3 counts. Count mode can trigger the entire range 1-15 counts.

As for SOCASELCMP being 0x0 will check the register again, it may be debug refresh cycle active for CMPD match count.

Also notice SOCASEL is set for CTR=PRD 0x010 and CMPD down count shadow load on Zero. Seems I opted for TBCTR=CMPD instead of TBCTR=ZERO.

EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE,
EPWM_COUNTER_COMPARE_D,
EPWM_COMP_LOAD_ON_CNTR_ZERO);

// setup the Event Trigger Selection Register (ETSEL)
EPWM_setADCTriggerSource(EPWM1_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_D_CMPD);

It seems the registers are reversed CCS Debug; ETSEL: SOCASEL and SOCASELCMP. Perhaps even the driverlib calls set the wrong register bits.

I don't think driverlib is setting the wrong register. Did updating the register values fix it?

Figure 18-47 ETSEL[SOCASELCMP] is a binary bit (1/0) in register ETSEL depending on what SOC A/B was selected. So debug view is somewhat confusing compared to Fig.18-47. Checking the TRM register ETSEL bit positions seems CCS debug (red boxes) are correct (0xF10). Unsure why interrupt generator mode did not have CMPD source in CCS register view.

SOCASELCMP is binary bit position 4 alone so it must have been interrupt generator mode making CMPB matches, though it was not configured. 

Yes it might have been that you have another function call that was overriding this setting back to ZERO.

Pulse generator mode works great for ADC SOC triggering even though ETFLG[SOCA] is latched pulses continue. Driverlib call mentions 1-15 maximum input value, but it left shifts input and ends up being 30 trigger count stored in register ETCNTINIT.  

Might also be good to clear pulse generator ETCLR[SOCA], versus interrupt ETCLR[INT] clearing. I was trying to find what causes motor to momentarily stall when EOC pulse vectors into ISR. Oddly a stall occurs after first 300ms of decimation pulses as the ISR returns back to startup while loop. The loop posts global updates to CCS debug watch window Java script and checks other constraints.