TMS320F28023: SCI peripheral problem of TMS320F28023

Hi Terrell,

Would it be possible for you to share how you have setup the SCI peripheral? Are you using FIFO, interrupts etc.

Have you measured what the actual baud rate is. You mentioned setting it to 600, but if you check with an oscilloscope, is it correct?

Best Regards,

Marlyn

Hi Marlyn，

I actually measured the baud rate，It's right，FIFO and interrupt are not used。SCI module configuration is as follows：

void ConfigScia(Uint32 baudrate)
{
Uint16 brr;

brr = (long)12500000 / baudrate / 8 - 1;

//config scia data format
SciaRegs.SCICCR.bit.ADDRIDLE_MODE = 0; // 0=Idle-Line mode, 1=Address-bit mode
SciaRegs.SCICCR.bit.SCICHAR = 7; // 8 char bits
SciaRegs.SCICCR.bit.PARITYENA = 0; // No parity
SciaRegs.SCICCR.bit.PARITY = 1; // 0=odd parity,1=even parity
SciaRegs.SCICCR.bit.STOPBITS = 0; // one stop bit

SciaRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,
                                                     // Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.all = 0x0000; // disable Tx & Rx interrupt

//baud rate
SciaRegs.SCIHBAUD = brr / 0xff; // 9600 baud @LSPCLK = 12.5MHz (50 MHz SYSCLK).
SciaRegs.SCILBAUD = brr % 0xff; //12500*1000/9600(baud rate)/8 -1 = 161 = 0xA1

SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset

//scia fifo
// SciaRegs.SCIFFTX.all = 0xE040;
// SciaRegs.SCIFFTX.all = 0x0040;
// SciaRegs.SCIFFRX.all = 0x2041;
SciaRegs.SCIFFCT.all = 0x0;
}

Hi Terrell,

Terrell Yang said:

I actually measured the baud rate，It's right

What was the measured baud rate of both devices? The framing error typically occurs when there is a miss-alignment in the baud rates or the communication line is not kept high when no communication is occurring. Please ensure both of these points are not the source of your issue.

Do you have any qualification setup for the SCI pins? Also, is the break detect flag getting set as well? 

Best Regards,

Marlyn

Hi Marlyn，

Baud rate of both devices are right，all 600。the communication line is kept high when no communication is occurring,

I have set GPIO28 and GPIO29 as SCI functions, and the break detect flag getting is not set。 

Hi Terrell,

Thank you for answering the questions. Do you have any kind of level shifters? What are the output rails of the other electronic device?

Best Regards,

Marlyn

Hi Marlyn，

I have no any kind of level shifters，and the other electronic device use SCI mode of R5F100JG chip。

In addition, I want to ask a question，if FE bit of SCIRXST is set to one, the DSP does not clear this bit，Can SCI module continue to receive data？

Hi Terrell,

Terrell Yang said:

if FE bit of SCIRXST is set to one, the DSP does not clear this bit，Can SCI module continue to receive data？

Yes, the SCI module will still continue to receive data even if there is an error detected.

Best Regards,

Marlyn

but I test if FE bit of SCIRXST is set to one，the SCI module can not continue to receive data immediately，need to wait for about 10s or even longer。

why?

if FE bit of SCIRXST is set to one, the DSP does not clear this bit，Can SCI module continue to Send data？

I use an oscilloscope to test the receiving and sending waveforms of DSP，when FE bit of SCIRXST is set to one，the SCI module can not continue to Sent data immediately，Because there is only received waveform, but no waveform is sent。need to wait for about 10s or even longer to communicate normally。

why?

Hi Terrell,

When the FE bit is set, you should so a SW reset of the SCI peripheral in order to clear the bit.

You mentioned that you are not using FIFOs or interrupts. When are you writing data? Is there a chance that the code is placed into a loop for some time when the FE bit is detected?

Best Regards,

Marlyn

Hi Marlyn，

I know how to clear FE bit，I just want to know if the FE bit is not cleared, Can SCI module receive and send data normally？

 The communication mechanism of this project is the master-slave relationship，Renesas chip is the host and 28023 chip is the slave。when 28023 receives the correct data and passes the verification， It sends data to Renesas chip with a delay of 50ms。

In the following figure, the waveform channel 3 is the transmission of Renesas chip, and the channel 1 is the reply of 28023 chip. When the fourth frame, 28023 detects the missing stop bit, and the 28023 chip will not reply to the data. After several consecutive cycles, Renesas chip sends, 28023 will not reply, and will reply after a period of time。

Hi Terrell,

Terrell Yang said:

I just want to know if the FE bit is not cleared, Can SCI module receive and send data normally？

The SCI should still be able to receive and send data normally in this scenario. 

Terrell Yang said:

After several consecutive cycles, Renesas chip sends, 28023 will not reply, and will reply after a period of time。

I suspect this might have something to do with how you have configured the code to send and receive data. Are you waiting for the data and checking if it is correct every time? Can you please explain the flow of how your software is written?

Best Regards,

Marlyn

Hi Marlyn，

    Are you waiting for the data and checking if it is correct every time? Can you please explain the flow of how your software is written?

Yes，The communication mechanism has been answered earlier，28023 chip is a slave， It must receive correct data and pass the verification

before it can send data。

Terrell,

Terrell Yang said:

 It must receive correct data and pass the verification

before it can send data。

Do you think this is what could be causing the extra delay before the F28023 device is capable of sending data again?

Best Regards,

Marlyn

Yes，I read the data in the SCIRXBUF register because I judged that the RXRDY bit in the SCIRXST register was one。

I use CCS compiler online simulation to check that when the FE bit is set to one, the RXRDY bit in the SCIRXST register will not be set one again for a period of time。

Hi Terrell,

Since this is part of your flow, that means the device is operating as is. If you are facing framing errors then this is something that needs to be resolved. 

Best Regards,
Marlyn

Hi Marlyn，

I have found and solved the cause of the frame error，I want to know why the SCI module cannot receive data normally when a frame error occurs?

You answered me earlier that when FE bit is set, SCI module can receive data normally。Now when FE bit  is set， the RXRDY bit in the SCIRXST register will not be set one again。Please tell me why？

Terrell,

       Marlyn is out of the office today, so please expect a delay of a day or two. 

Terrell,

Terrell Yang said:

I have found and solved the cause of the frame error

What was the issue?

Terrell Yang said:

when FE bit  is set， the RXRDY bit in the SCIRXST register will not be set one again

I will consult with our design team and provide an update on this as soon as I can. 

Best Regards,

Marlyn