F28M35H52C: F28M35H52C Failed to read external RAM register data.

I regret I am unable to understand what you are saying. Could you please elaborate?

1. As shown in the figure above,TI MCU F28M35 official routine epi_sram_8bit found configuration EPIOS31-- A20 usage not quite understand, why in the reading time need to pull up pull down, and configuration time need to configure the output mode, HB8 mode does not exist A20, why so use? 

2. If I am using HB16 now, I also need to use A12, but I actually find only A11, how should I deal with it? Can I also choose the following pins to deal with it according to the routine?  Please inform me, thank you very much!  

FYI

zhanxing wu said:

1.TI MCU F28M35 official routine epi_sram_8bit found configuration EPIOS31-- A20 usage not quite understand, why in the reading time need to pull up pull down, and configuration time need to configure the output mode, HB8 mode does not exist A20, why so use?  

For HB8 mode, A20 is used in Muxed mode. However, it is not available in Non-Muxed mode, since the number of address pins is reduced (stops at A19). I presume your question is why we initialize EPIOS31 when A20 is not available in HB8 mode, correct? For example, the following lines refer to this signal: 61, 158 & 524.

I think A20 is being used to double the memory that can be accessed. i.e. A20 is used select a different page of memory. 

Could you please point me to the version of ControlSuite you are using? I am using v220.

zhanxing wu said:

2. If I am using HB16 now, I also need to use A12, but I actually find only A11, how should I deal with it? Can I also choose the following pins to deal with it according to the routine?

In the non-muxed mode, the address range is reduced and only 12 address pins are available (A0-A11). You may be able to use a GPIO pin as A12, similar to how A20 is being used in HB8 mode.

zhanxing wu said:

3. In addition, there is a problem that when PJ4_GPIO60 is used as the external RAM read and write command, it can read the value of the external RAM register only by shorting it to 3V3, but not by simply pulling up. Why is this?

Sorry I don’t understand. Can you please share your schematics with me?

1,The TI controlSUITE version I use is V202,The epI_SRAM_8bit is shown below,The screenshot of my configuration when accessing DPRAM using HB16 is also shown below.

I found 14 address lines in the DPRAM,and I pulled down A0 of the DPRAM ,So the A13 on the DPRAM side needs to connect to the A12 on the F28M35,but the actual EPI doesn't have A12,I looked at the official routine and found that we can configure address lines that are not defined by the EPI ,The official routine:

GPIOPinWrite（GPIO_PORTG_BASE，GPIO_PIN_7，0，

GPIOPinWrite（GPIO_PORTG_BASE，GPIO_PIN_7，1,

So I wonder if the official routine means to read the memory of different blocks of external RAM?  Do I need to operate in this way when I use it? 

For example, suppose I define address line A12 as G6,

GPIOPinWrite（GPIO_PORTG_BASE，GPIO_PIN_6，0）,This allows access to register addresses up to 0x1000;

GPIOPinWrite（GPIO_PORTG_BASE，GPIO_PIN_6，1）,This allows access to register addresses above 0x1000;

Is the above statement true?

2,When I access the 0x204 address of the external DPRAM based on the configuration below,I found that only by shorting RD pin and 3.3V can I read the data, otherwise the data I read is wrong, can you explain the reason?

I need a day or two to analyze this. Thank you for your patience.

Hi, is there any good news？

zhanxing wu said:

1. As shown in the figure above,TI MCU F28M35 official routine epi_sram_8bit found configuration EPIOS31-- A20 usage not quite understand, why in the reading time need to pull up pull down, and configuration time need to configure the output mode, HB8 mode does not exist A20, why so use?

The example was written to interface the EPI to the IS61WV20488BLL chip, which is a 2M x 8 device. To address 2M locations, you need 21 address lines. However, in the non-muxed mode, A20 is not available. Therefore, EPI0S31 is likely being used to emulate A20 pin via software.

zhanxing wu said:

2. If I am using HB16 now, I also need to use A12, but I actually find only A11, how should I deal with it? Can I also choose the following pins to deal with it according to the routine?

In the non-muxed mode, the address range is reduced and only 12 address pins are available (A0-A11). You may be able to use an unused EPI0S pin as A12, similar to how EPI0S31 is being used as A20 in HB8 mode.

zhanxing wu said:

The TI controlSUITE version I use is V202,

If possible, please download the most recent version, which is v220

zhanxing wu said:

I found 14 address lines in the DPRAM,and I pulled down A0 of the DPRAM ,So the A13 on the DPRAM side needs to connect to the A12 on the F28M35,but the actual EPI doesn't have A12

Could you please send me the complete schematics? I have a hard time understanding your issue. You don’t have to post it on the forum; you can share it with me privately by initiating a “friendship” request. At the very least, I need to see all the connections between the MCU and your memory chip.

Zhanxing,

    On a slightly different note, do your questions pertain to an existing design/project that is in production or are they about a new project?